Abov A96G174 - Interrupt Timing; Interrupt Register Overview; Interrupt Enable Register (IE, IE1, and IE2); Interrupt Priority Register (IP and IP1)

7. Interrupt controller A96G174/A96S174 User’s manual
64
7.11 Interrupt timing
NOTE: Variable x and n of a command cycle CLPx imply the followings:
 x ➔ Last cycle, 1
st
cycle, 2
nd
cycle
 n ➔ 1
st
phase, 2
nd
phase
Figure 26. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the
lower 8-bit of interrupt vector (INT_VEC) is decided. M8051W core makes interrupt acknowledge at the
first cycle of a command, and executes long call to jump to interrupt service routine.
7.12 Interrupt register overview
7.12.1 Interrupt Enable Register (IE, IE1, and IE2)
Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits.
Total 14 peripherals are able to control interrupt.
7.12.2 Interrupt Priority Register (IP and IP1)
14 interrupts are divided into 2 groups which have 6 interrupt sources respectively. A group can be
assigned to 4 levels of interrupt priority using interrupt priority register. Level 3 is the highest priority,
while level 0 is the lowest priority.
CLP2
CLP1
C2P1
C1P1
C2P2
C1P2
CLP2
Interrupt sampled here
8-bit interrupt Vector
INT_SRC
INTR_ACK
LAST_CYC
INTR_LCALL
INT_VEC
PROGA
SCLK