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Abov A96G174 - 10 Watchdog Timer

Abov A96G174
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A96G174/A96S174 User’s manual 10. Watchdog timer
73
10 Watchdog timer
The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or
something like that, and resumes the CPU to the normal state. The watchdog timer signal for
malfunction detection can be used as either a CPU reset or an interrupt request. When the watchdog
timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at
fixed intervals. When 75% of the overflow time is reached, a watchdog interrupt can be generated. The
overflow time of the watchdog timer can select by WDTOVF[2:0] of WDTCR. If an overflow occurs, an
internal reset is generated. The WDTRC operation in the STOP/IDLE mode differs as follows depending
on the setting value of WDTPDON. If WDTPDON = 0, the WDTRC operation stop in the STOP/IDLE
mode and if WDTPDON = 1, the WDTRC operation in the STOP/IDLE mode. The watchdog timer
operate on the 4kHz, based on clock 128kHz Ring oscillator clock.
Watchdog reset is occurred in the following cases:
When the watchdog timer counter overflows
When the data except “96H” is written to the WDTC register
When the data “96H” is written to the WDTC register during a window close period

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