Abov A96G174 - Table of Contents

Contents A96G174/A96S174 User’s manual
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Contents
Introduction.............................................................................................................................................. 1
Reference document ............................................................................................................................... 1
1 Description ................................................................................................................................... 11
1.1 Device overview .................................................................................................................. 11
1.2 A96G174/A96S174 block diagram...................................................................................... 13
2 Pinouts and pin description .......................................................................................................... 14
2.1 Pinouts ................................................................................................................................ 14
2.2 Pin description..................................................................................................................... 20
3 Port structures .............................................................................................................................. 23
4 Central Processing Unit(CPU) ..................................................................................................... 25
4.1 Architecture and registers ................................................................................................... 25
4.2 Addressing .......................................................................................................................... 27
4.3 Instruction set ...................................................................................................................... 28
5 Memory organization .................................................................................................................... 30
5.1 Program memory ................................................................................................................ 30
5.2 Data memory ....................................................................................................................... 31
5.3 External data memory ......................................................................................................... 34
5.4 SFR map ............................................................................................................................. 35
5.4.1 SFR map summary ................................................................................................ 35
5.4.2 SFR map ................................................................................................................ 37
5.4.3 Compiler compatible SFR ...................................................................................... 41
6 I/O ports ....................................................................................................................................... 43
6.1 Port register ......................................................................................................................... 43
6.1.1 Data register (Px) ................................................................................................... 43
6.1.2 Direction register (PxIO) ......................................................................................... 43
6.1.3 Pull-up register selection register (PxPU) .............................................................. 43
6.1.4 Open-drain Selection Register (PxOD) .................................................................. 43
6.1.5 De-bounce Enable Register (PxDB) ...................................................................... 43
6.1.6 Port Function Selection Register (PxFSR) ............................................................. 43
6.1.7 Register Map .......................................................................................................... 44
6.2 P0 port ................................................................................................................................. 45
6.2.1 P0 port description ................................................................................................. 45
6.2.2 Register description for P0 ..................................................................................... 45
6.3 P1 port ................................................................................................................................. 49
6.3.1 P1 port description ................................................................................................. 49
6.3.2 Register description for P1 ..................................................................................... 49
6.4 P2 port ................................................................................................................................. 53
6.4.1 P2 port description ................................................................................................. 53
6.4.2 Register description for P2 ..................................................................................... 53
7 Interrupt controller ........................................................................................................................ 55
7.1 External interrupt ................................................................................................................. 56
7.2 Pin Change Interrupt ........................................................................................................... 57
7.3 Block diagram ..................................................................................................................... 58
7.4 Interrupt vector table ........................................................................................................... 59
7.5 Interrupt sequence .............................................................................................................. 60
7.6 Effective timing after controlling interrupt bit ....................................................................... 61
7.7 Multi-interrupt ...................................................................................................................... 62