Abov A96G174 - Register Description

10. Watchdog timer A96G174/A96S174 User’s manual
76
10.4 Register description
WDTCNTH (Watch Dog Timer Counter High Register: Read Case): 1012H
7
6
5
4
3
2
1
0
WDTCNT 15
WDTCNT 14
WDTCNT 13
WDTCNT 12
WDTCNT11
WDTCNT 10
WDTCNT 9
WDTCNT 8
R
R
R
R
R
R
R
R
Initial value: 00H
WDTCNT[15:8]
WDT Counter
WDTCNTL (Watch Dog Timer Counter Low Register: Read Case): 1013H
7
6
5
4
3
2
1
0
WDTCNT 7
WDTCNT 6
WDTCNT 5
WDTCNT 4
WDTCNT3
WDTCNT 2
WDTCNT 1
WDTCNT 0
R
R
R
R
R
R
R
R
Initial value: 00H
WDTCNT[7:0]
WDT Counter
WDTC (Watch Dog Timer Clear Register): 1010H
7
6
5
4
3
2
1
0
WDTC 7
WDTC6
WDTC5
WDTC 4
WDTC3
WDTC 2
WDTC 1
WDTC 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
WDTC[7:0]
WDT Counter clear
Others Reset occurs.
10010110 WDT counter clear and start again.
WDTSR (Watch Dog Timer Status Register): 1011H
7
6
5
4
3
2
1
0
–
–
–
–
–
–
WSTATE
WDTIFR
–
–
–
–
–
–
R
R/W
Initial value: 00H
WSTATE
Window Status
0
Close window
1
Open window
WDTIFR
When WDT Interrupt occurs, this bit becomes ‘1’. For clearing bit,
Write ‘0’ to this bit or auto clear by INT_ACK signal.
0
WDT Interrupt no generation
1
WDT Interrupt generation