Abov A96G174 - Register Map; Register Description; Table 10. Clock Generator Register Map

8. Clock generator A96G174/A96S174 User’s manual
70
8.2 Register map
Table 10. Clock Generator Register Map
Name
Address
Direction
Default
Description
SCCR
8AH
R/W
00H
System and Clock Control Register
OSCCR
C8H
R/W
28H
Oscillator Control Register
8.3 Register description
SCCR (System and Clock Control Register): 8AH
7
6
5
4
3
2
1
0
–
–
–
–
–
–
SCLK1
SCLK0
–
–
–
–
–
–
R/W
R/W
Initial value: 00H
SCLK [1:0]
System Clock Selection Bit
SCLK1
SCLK0
Description
0
0
Internal 32MHz RC OSC (f
HSIRC
) for system clock
0
1
Internal 128kHz RC OSC (f
LSIRC)
for system clock
1
0
Reserved
1
1
Reserved
OSCCR (Oscillator Control Register): C8H
7
6
5
4
3
2
1
0
–
LSIRCE
IRCS2
IRCS1
IRCS0
HSIRCE
–
–
–
R/W
R/W
R/W
R/W
R/W
–
–
Initial value: 28H
LSIRCE
Control the Operation of the Low Frequency (128kHz) internal RC Oscillator at Stop mode
0
Disable operation of LSIRC OSC
1
Enable operation of LSIRC OSC
IRCS[2:0]
Internal RC Oscillator Post-divider Selection
IRCS2
IRCS1
IRCS0
Description
0
0
0
INT-RC/64 (0.5MHz)
0
0
1
INT-RC/32 (1MHz)
0
1
0
INT-RC/16 (2MHz)
0
1
1
INT-RC/8 (4MHz)
1
0
0
INT-RC/4 (8MHz)
1
0
1
INT-RC/2 (16MHz)
1
1
0
Test only
Other Values
reserved
HSIRCE
Control the Operation of the High Frequency (32MHz) Internal RC Oscillator
0
Enable operation of HSIRC OSC
1
Disable operation of HSIRC OSC