11.2 Timer 1
A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low
and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL, T1DRH,
T1DRL).
Timer 1 operates in one of the following modes:
16-bit timer/counter mode
16-bit capture mode
16-bit PPG output mode (one-shot mode)
16-bit PPG output mode (repeat mode)
The timer/counter 1 uses an internal clock or an external clock (EC1) as an input clock source. The
clock sources are introduced below, and one is selected by clock selection logic which is controlled by
clock selection bits (T1CK[2:0]).
TIMER 1 clock source: fX/1, 2, 4, 8, 64, 2048, HFO and EC1
In capture mode, the data is captured into input capture data register (T1BDRH/T1BDRL) by EINT11.
Timer 1 results in the comparison between counter and data register through T1O port in timer/counter
mode. In addition, Timer 1 outputs PWM waveform through PWM1Oport in the PPG mode.
Table 16. TIMER 1 Operating Modes
11.2.1 16-bit timer/counter mode
16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter
registers and data registers as shown in Figure 39. The counter register is increased by internal or
external clock input. Timer 1 can use the input clock with one of 1, 2, 4, 8, 64, 2048 and Internal High
Frequency Oscillator (HFO) prescaler division rates (T1CK[2:0]). When the value of T1CNTH, T1CNTL
and the value of T1ADRH, T1ADRL are identical to each other in Timer 1, a match signal is generated
and the interrupt of Timer1 occurs. The T1CNTH, T1CNTL value is automatically cleared by the match
signal. It can be cleared by software (T1CC) too.
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