A96G174/A96S174 User’s manual 5. Memory organization
Table 5. SFR Map (continued)
External Interrupt Flag 0 Register
Timer 2 Control Low Register
Timer 2 Control High Register
Timer 2 A Data Low Register
Timer 2 A Data High Register
Timer 2 B Data Low Register
Timer 2 B Data High Register
Oscillator Control Register
Program Status Word Register
P0 Function Selection Low Register
P0 Function Selection High Register
P1 Function Selection Low Register
P1 Function Selection High Register
P2 Function Selection Register
Low Voltage Reset Control Register
P1/P5 De-bounce Enable Register
I2C Mode Control Register
I2C Slave Address Register
I2C Slave Address Register 1
Interrupt Priority Register 1
USART Baud Rate Generation Register