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Abov A96G174 - Table 5. SFR Map (Continued)

Abov A96G174
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A96G174/A96S174 User’s manual 5. Memory organization
39
Table 5. SFR Map (continued)
Address
Function
Symbol
R/W
@Reset
7
6
5
4
3
2
1
0
C0H
External Interrupt Flag 0 Register
EIFLAG0
R/W
0
0
0
0
0
0
0
0
C2H
Timer 2 Control Low Register
T2CRL
R/W
0
0
0
0
–
0
–
0
C3H
Timer 2 Control High Register
T2CRH
R/W
0
–
0
0
–
–
–
0
C4H
Timer 2 A Data Low Register
T2ADRL
R/W
1
1
1
1
1
1
1
1
C5H
Timer 2 A Data High Register
T2ADRH
R/W
1
1
1
1
1
1
1
1
C6H
Timer 2 B Data Low Register
T2BDRL
R/W
1
1
1
1
1
1
1
1
C7H
Timer 2 B Data High Register
T2BDRH
R/W
1
1
1
1
1
1
1
1
C8H
Oscillator Control Register
OSCCR
R/W
–
0
1
0
1
0
0
0
CBH
USART Control Register 1
UCTRL1
R/W
0
0
0
0
0
0
0
0
CCH
USART Control Register 2
UCTRL2
R/W
0
0
0
0
0
0
0
0
CDH
USART Control Register 3
UCTRL3
R/W
0
0
0
0
–
0
0
0
CFH
USART Status Register
USTAT
R/W
1
0
0
0
0
0
0
0
D0H
Program Status Word Register
PSW
R/W
0
0
0
0
0
0
0
0
D2H
P0 Function Selection Low Register
P0FSRL
R/W
0
0
0
0
0
0
0
0
D3H
P0 Function Selection High Register
P0FSRH
R/W
0
0
0
0
0
0
0
0
D4H
P1 Function Selection Low Register
P1FSRL
R/W
0
0
0
0
0
0
0
0
D5H
P1 Function Selection High Register
P1FSRH
R/W
0
0
0
0
0
0
0
0
D6H
P2 Function Selection Register
P2FSR
R/W
–
–
–
0
0
0
0
0
D8H
Low Voltage Reset Control Register
LVRCR
R/W
–
–
–
0
0
0
0
0
DFH
P1/P5 De-bounce Enable Register
P15DB
R/W
–
–
0
0
0
0
0
0
E0H
Accumulator Register
ACC
R/W
0
0
0
0
0
0
0
0
E1H
I2C Mode Control Register
I2CMR
R/W
0
0
0
0
0
0
0
0
E2H
I2C Status Register
I2CSR
R
0
0
0
0
0
0
0
0
E3H
SCL Low Period Register
I2CSCLLR
R/W
0
0
1
1
1
1
1
1
E4H
SCL High Period Register
I2CSCLHR
R/W
0
0
1
1
1
1
1
1
E5H
SDA Hold Time Register
I2CSDAHR
R/W
0
0
0
0
0
0
0
1
E6H
I2C Data Register
I2CDR
R/W
1
1
1
1
1
1
1
1
E9H
I2C Slave Address Register
I2CSAR
R/W
0
0
0
0
0
0
0
0
EAH
I2C Slave Address Register 1
I2CSAR1
R/W
0
0
0
0
0
0
0
0
E8H
Reset Flag Register
RSTFR
R/W
1
x
0
0
x
–
–
–
F0H
B Register
B
R/W
0
0
0
0
0
0
0
0
F8H
Interrupt Priority Register 1
IP1
R/W
–
–
0
0
0
0
0
0
FCH
USART Baud Rate Generation Register
UBAUD
R/W
1
1
1
1
1
1
1
1
FDH
USART Data Register
UDATA
R/W
0
0
0
0
0
0
0
0

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