Abov A96G174 - WDT Block Diagram; Register Map; Figure 30. Watch Dog Timer Block Diagram; Table 12. Watch Dog Timer Register Map

A96G174/A96S174 User’s manual 10. Watchdog timer
75
Table 12. Watch Dog Timer Register Map
Setting of window open period
Window close period
Window open period
50%, WINDOW[1:0]=00b & WDTPDON = 1
50%
50%
75%, WINDOW[1:0]=01b & WDTPDON = 1
25%
75%
100%, WINDOW[1:0]=10b & WDTPDON = 1
WDTCNT = “0000H”
100%
100%, WDTPDON = 0
WDTCNT = “0000H”
100%
10.2 WDT block diagram
75 % Interval
Controller
WDTCR
WDTEN
To RESET
Circuit
WDTIFR
To interrupt
block
INT_ACK
clear
WDTIDR
WDTC
Overflow Time
Selector
WDOVF[2:0]
Check
Identification
Window
Selector
WDTPDON
clear
WDTRTI
WINDOW[1:0]
INTERNAL BUS
8
8
WDT Clock
(TYP 4KHz)
stop/idle
DIV/32
WDT16-Bit CNT
Write detector to
WDTE except 96H
fLSIRC
=128KHz
Figure 30. Watch Dog Timer Block Diagram
10.3 Register map
Table 13. Watchdog Timer Register Map
Name
Address
Direction
Default
Description
WDTC
1010H
R/W
00H
Watch Dog Timer Clear Register
WDTSR
1011H
R/W
00H
Watch Dog Timer Status Register
WDTIDR
8EH
W
00H
Watch Dog Timer Identification Register
WDTCR
8DH
R/W
07H
Watch Dog Timer Control Register
WDTCNTH
1012H
R
00H
Watch Dog Timer Count H Register
WDTCNTL
1013H
R
00H
Watch Dog Timer Count L Register