5 Memory organization
A96G174/A96S174 addresses two separate memory spaces:
Program memory
Data memory
By means of this logical separation of the memory, 8-bit CPU address can access the Data Memory
more rapidly. 16-bit Data Memory address is generated through the DPTR register.
A96G174/A96S174 provides on-chip 8Kbytes of the ISP type flash program memory, which readable
and writable. Internal data memory (IRAM) is 256bytes and it includes the stack area. External data
memory (XRAM) is 256bytes.
5.1 Program memory
A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G174/A96S174 has just
8Kbytes program memory space.
Figure 11 shows a map of the lower part of the program memory.
After reset, CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in
the program memory. An interrupt causes the CPU to jump to the corresponding location, where it
commences execution of the service routine.
An external interrupt 11, for example, is assigned to location 000BH. If the external interrupt 11 is going
to be used, its service routine must begin at location 000BH. If the interrupt is not going to be used, its
service location is available as general purpose program memory. If an interrupt service routine is short
enough (as is often the case in control applications), it can reside entirely within an interval of 8-bytes.
Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other
interrupts are in use.
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