Abov A96G174 - 16-Bit Timer 1 Block Diagram; Register Map; Figure 48. 16-Bit Timer 1 Block Diagram; Table 17. TIMER 1 Register Map

A96G174/A96S174 User’s manual 11. Timer 0/1/2
95
11.2.5 16-bit timer 1 block diagram
In this section, a 16-bit timer 1 is described in a block diagram.
T1MS[1:0]
T1POL
Reload
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
fx/4
fx/64
fx/2048
fx/8
fx/1
Comparator
16-bit Counter
T1CNTH/T1CNTL
16-bit B Data Register
T1BDRH/T1BDRL
Clear
B Match
Edge
Detector
T1ECE
EC1
Buffer Register B
Comparator
16-bit A Data Register
T1ADRH/T1ADRL
T1IFR
INT_ACK
Clear
To interrupt
block
A Match
Buffer Register A
Reload
Pulse
Generator
T1O/
PWM1O
R
T1EN
3
T1CK[2:0]
2
T1PE
A Match
T1CC
T1EN
16-bit C Data Register
T1CDRH/T1CDRL
Buffer Register C
T1BPOL
Pulse
Generator
PWM1OB
2
T1BEN
C Match
Reload
16-bit Counter
TZCNTH/TZCNT
16-bit D Data Register
T1DDRH/T1DDRL
Buffer Register D
Reload
R
D Match
EINT1
T1CNTR
EIPOL[3:2]
2
T1MS[1:0]
2
FLAG1
(EIFLAG.1)
INT_ACK
Clear
To interrupt
block
HSIRC
Figure 48. 16-bit Timer 1 Block Diagram
11.2.6 Register map
Table 17. TIMER 1 Register Map
Name
Address
Direction
Default
Description
T1ADRH
BDH
R/W
FFH
Timer 1 A Data High Register
T1ADRL
BCH
R/W
FFH
Timer 1 A Data Low Register
T1BDRH
BFH
R/W
FFH
Timer 1 B Data High Register
T1BDRL
BEH
R/W
FFH
Timer 1 B Data Low Register
T1CDRL
D9H
R/W
FFH
Timer 1 C Data Low Register
T1CDRH
DAH
R/W
FFH
Timer 1 C Data High Register
T1DDRL
DBH
R/W
FFH
Timer 1 D Data Low Register
T1DDRH
DCH
R/W
FFH
Timer 1 D Data High Register
T1CRL
BAH
R/W
00H
Timer 1 Control Low Register
T1CRH
BBH
R/W
00H
Timer 1 Control High Register