Abov A96G174 - BIT Register Description

9. Basic interval timer A96G174/A96S174 User’s manual
72
9.3 BIT register description
BITCNT (Basic Interval Timer Counter Register): 8CH
7
6
5
4
3
2
1
0
BITCNT7
BITCNT6
BITCNT5
BITCNT4
BITCNT3
BITCNT2
BITCNT1
BITCNT0
R
R
R
R
R
R
R
R
Initial value: 00H
BITCNT[7:0]
BIT Counter
BITCR (Basic Interval Timer Control Register): 8BH
7
6
5
4
3
2
1
0
BITIFR
BITCK2
BITCK1
BITCK0
BCLR
BCK2
BCK1
BCK0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 45H
BITIFR
When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to
this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
0
BIT interrupt no generation
1
BIT interrupt generation
BITCK[2:0]
Select BIT clock source
BITCK2
BITCK1
BITCK0
Description
0
0
0
fx/4096
0
0
1
fx/1024
0
1
0
fx/128
0
1
1
fx/16
1
Other Values
LSIRC/32 (Default)
BCLR
If this bit is written to ‘1’, BIT Counter is cleared to ‘0’
0
Free Running
1
Clear Counter
BCK[2:0]
Select BIT overflow period
BCK2
BCK1
BCK0
Description (fx=LSIRC 128k)
0
0
0
0.5ms (BIT Clock * 2)
0
0
1
1ms (BIT Clock * 4)
0
1
0
2ms (BIT Clock * 8)
0
1
1
4ms (BIT Clock * 16)
1
0
0
8ms (BIT Clock * 32)
1
0
1
16ms (BIT Clock * 64) (default)
1
1
0
32ms (BIT Clock * 128)
1
1
1
64ms (BIT Clock * 256)