7 Interrupt controller
A96G174/A96S174 supports up to 14 interrupt sources. The interrupts have separate enable register
bits associated with them, allowing software control. In addition, they have four levels of priority
assigned to themselves.
A non-maskable interrupt source is always enabled with a higher priority than any other interrupt
sources, and is not controllable by software.
Interrupt controller of A96G174/A96S174 has following features:
Request receive from the 14 interrupt sources
2 groups of priority
4 levels of priority
Multi Interrupt possibility
A request of higher priority level is served first, when multiple requests of different priority
levels are received simultaneously.
Each interrupt source can be controlled by EA bit and each IEx bit
Interrupt latency of 3 to 9 machine cycles in single interrupt system
A non-maskable interrupt is always enabled, while maskable interrupts are enabled through four pairs
of interrupt enable registers (IE, IE1, IE2, and IE3). Each bit of IE, IE1, IE2, IE3 register individually
enables/disables the corresponding interrupt source. Overall control is provided by bit 7 of IE (EA).
When EA is set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled
or disabled through the other bits of the interrupt enable registers. The EA bit is always cleared to ‘0’
jumping to an interrupt service vector and set to ‘1’ executing the [RETI] instruction. The
A96G174/A96S174 supports a four-level priority scheme. Each maskable interrupt is individually
assigned to one of four priority levels according to IP and IP1.
Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-
trigger mode. Figure 15 shows the Interrupt Group Priority Level that is available for sharing interrupt
priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IP, another one
from IP1). Interrupt service routine serves higher priority interrupt first. If two requests of different priority
levels are received simultaneously, the request of higher priority level is served prior to the lower one.
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