Abov A96G174 - ADC Operation; Figure 59. Control Registers and Align Bits

12. 12-bit ADC A96G174/A96S174 User’s manual
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12.3 ADC operation
In this section, control registers and align bits are introduced in Figure 59, and ADC operation flow
sequence is introduced in Figure 60.
Align bit set “0”
ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4
ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
Align bit set “1”
ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0
ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0
ADCDRL[7:0]
ADCDRL[3:0]
ADCDRL[7:4] bits are “0”
ADCDRH[7:0]
ADCDRL[7:4]
ADCDRL[3:0] bits are “0”
Figure 59. Control Registers and Align Bits