Abov A96G174 - Basic Interval Timer; BIT Block Diagram; BIT Register Map; Figure 28. Basic Interval Timer Block Diagram

A96G174/A96S174 User’s manual 9. Basic interval timer
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9 Basic interval timer
A96G174/A96S174 has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for
watchdog timer counting, and provides a basic interval timer interrupt (BITIFR).
BIT of A96G174/A96S174 features the followings:
 During Power On, BIT gives a stable clock generation time
 On exiting Stop mode, BIT gives a stable clock generation time
 As a timer, BIT generates a timer interrupt.
9.1 BIT block diagram
In this section, basic interval timer of A96G174/A96S174 is described in a block diagram.
/32
Prescaler
1/4096
1/16
1/1024
1/128
3
BITCK
BITCNT BITIFR
Overflow
8-bit up-counter
BITCR
INT_ACK
From CPU
Interal BUS line
BCLR
Read
BIT Interrupt
[8B
H
]
[8C
H
]
fx
(System Clock)
LIRC OSC
(128kHz)
BIT_CLK
0 1 2 3
4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
BITR
BIT_Int_Flag
BIT_Out
 BCK[2:0] = 001b
Figure 28. Basic Interval Timer Block Diagram
9.2 BIT register map
Table 11. Basic Interval Timer Register Map
Name
Address
Direction
Default
Description
BITCNT
8CH
R
00H
Basic Interval Timer Counter Register
BITCR
8BH
R/W
45H
Basic Interval Timer Control Register