Abov A96G174 - Connection of Transmission; Figure 113. Connection of Transmission

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A96G174/A96S174 User’s manual Development tools

201

18.6 Connection of transmission

OCD’s two-wire communication interfaces use the Open-Drain Method (Wire-AND Bi-Directional I/O).

Normally, it is recommended to place a resister greater than 4.7kΩ for the DSCL and DSDA respectively.

The capacitive load is recommended to be less than 100pF. Outside these ranges, because the

communication may not be accomplished, the connection to Debug mode is not guaranteed.

Figure 113. Connection of Transmission

Main Page

Introduction1
Reference Document1
Table of Contents2
Description11
Device Overview11
Table 1. A96G174/A96S174 Device Features and Peripheral Counts11
Table 1. A96G174/A96S174 Device Features and Peripheral Counts (Continued)12
A96G174/A96S174 Block Diagram13
Figure 1. A96G174/A96S174 Block Diagram13
Pinouts and Pin Description14
Pinouts14
Figure 2. A96G174 20TSSOP Pin Assignment14
Figure 3. A96S174 20TSSOP Pin Assignment15
Figure 4. A96G174 20SOP Pin Assignment16
Figure 5. A96G174 20QFN Pin Assignment17
Figure 6. A96S174 20QFN Pin Assignment18
Figure 7. A94G174 16SOPN Pin Assignment19
Pin Description20
Table 2. Normal Pin Description20
Table 2. Normal Pin Description (Continued)21
Table 2. Normal Pin Description (Continued)22
Port Structures23
Figure 8. General Purpose I/O Port23
Figure 9. External Interrupt I/O Port24
Central Processing Unit(CPU)25
Architecture and Registers25
Figure 10. M8051EW Architecture25
Addressing27
Instruction Set28
Memory Organization30
Program Memory30
Data Memory31
Figure 11. Program Memory Map31
Figure 12. Data Memory Map32
Figure 13. Lower 128Bytes of RAM33
External Data Memory34
Figure 14. XDATA Memory Area34
SFR Map35
SFR Map Summary35
Table 3. SFR Map Summary35
Table 4. XSFR Map Summary36
SFR Map37
Table 5. SFR Map37
Table 5. SFR Map (Continued)38
Table 5. SFR Map (Continued)39
Table 6. XSFR Map40
Compiler Compatible SFR41
6 I/O Ports43
Port Register43
Data Register (Px)43
Direction Register (Pxio)43
Pull-Up Register Selection Register (Pxpu)43
Open-Drain Selection Register (Pxod)43
Bounce Enable Register (Pxdb)43
Port Function Selection Register (Pxfsr)43
Register Map44
Table 7. Port Register Map44
P0 Port45
P0 Port Description45
Register Description for P045
P1 Port49
P1 Port Description49
Register Description for P149
P2 Port53
P2 Port Description53
Register Description for P253
Interrupt Controller55
External Interrupt56
Figure 15. Interrupt Group Priority Level56
Figure 16. External Interrupt Description56
Pin Change Interrupt57
Figure 17. Pin Change Interrupt57
Block Diagram58
Figure 18. Interrupt Controller Block Diagram58
Interrupt Vector Table59
Table 8. Interrupt Vector Address Table59
Interrupt Sequence60
Figure 19. Interrupt Sequence Flow60
Effective Timing after Controlling Interrupt Bit61
Figure 20. Effective Timing of Interrupt Enable Register61
Figure 21. Effective Timing of Interrupt Flag Register61
Multi-Interrupt62
Figure 22. Effective Timing of Multi-Interrupt62
Interrupt Enable Accept Timing63
Interrupt Service Routine Address63
Saving/Restore General Purpose Registers63
Figure 23. Interrupt Response Timing Diagram63
Figure 24. Correspondence between Vector Table Address and the Entry Address of ISR63
Figure 25. Saving/Restore Process Diagram and Sample Source63
Interrupt Timing64
Interrupt Register Overview64
Interrupt Enable Register (IE, IE1, and IE2)64
Interrupt Priority Register (IP and IP1)64
Figure 26. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction64
External Interrupt Flag Register (EIFLAG0 and EIFLAG1)65
External Interrupt Polarity Register (EIPOL0L, EIPOL0H, and EIPOL1)65
Register Map65
Table 9. Interrupt Register Map65
Interrupt Register Description66
Clock Generator69
Clock Generator Block Diagram69
Figure 27. Clock Generator Block Diagram69
Register Map70
Register Description70
Table 10. Clock Generator Register Map70
Basic Interval Timer71
BIT Block Diagram71
BIT Register Map71
Figure 28. Basic Interval Timer Block Diagram71
Table 11. Basic Interval Timer Register Map71
BIT Register Description72
10 Watchdog Timer73
Setting Window Open Period of Watchdog Timer74
Figure 29. Watch Dog Timer Interrupt Timing Waveform74
WDT Block Diagram75
Register Map75
Figure 30. Watch Dog Timer Block Diagram75
Table 12. Watch Dog Timer Register Map75
Table 13. Watchdog Timer Register Map75
Register Description76
Timer 0/1/278
Timer 078
8-Bit Timer/Counter Mode78
Table 14. Timer 0 Operating Mode78
Figure 31. 8-Bit Timer/Counter Mode for Timer 079
Figure 32. 8-Bit Timer/Counter 0 Example79
8-Bit PWM Mode80
Figure 33. 8-Bit PWM Mode for Timer 080
Figure 34. PWM Output Waveforms in PWM Mode for Timer 081
8-Bit Capture Mode82
Figure 35. 8-Bit Capture Mode for Timer 082
Figure 36. Input Capture Mode Operation for Timer 083
Figure 37. Express Timer Overflow in Capture Mode83
Timer 0 Block Diagram84
Register Map84
Figure 38. 8-Bit Timer 0 Block Diagram84
Table 15. Timer 0 Register Map84
Register Description85
Timer 187
16-Bit Timer/Counter Mode87
Table 16. TIMER 1 Operating Modes87
Figure 39. 16-Bit Timer/Counter Mode of Timer 188
Figure 40. 16-Bit Timer/Counter Mode Operation Example88
16-Bit Capture Mode89
Figure 41. 16-Bit Capture Mode of Timer 189
Figure 42. Input Capture Mode Operation for Timer190
Figure 43. Express Timer Overflow in Capture Mode90
16-Bit PPG Mode91
Figure 44. 16-Bit PPG Mode of Timer 191
Figure 45. 16-Bit PPG Mode Operation Example92
16-Bit Complementary PWM Mode (Dead Time)93
Figure 46. 16-Bit Complementary PWM Mode for Timer193
Figure 47. 16-Bit Complementary PWM Mode Timing Chart for Timer 194
16-Bit Timer 1 Block Diagram95
Register Map95
Figure 48. 16-Bit Timer 1 Block Diagram95
Table 17. TIMER 1 Register Map95
Register Description96
Timer 299
16-Bit Timer/Counter Mode99
Table 18. TIMER 2 Operating Modes99
Figure 49. 16-Bit Timer/Counter Mode of Timer 2100
Figure 50. 16-Bit Timer/Counter Mode Operation Example100
16-Bit Capture Mode101
Figure 51. 16-Bit Capture Mode of Timer 2101
Figure 52. 16-Bit Capture Mode Operation Example102
Figure 53. Express Timer Overflow in Capture Mode102
16-Bit PPG Mode103
Figure 54. 16-Bit PPG Mode of Timer 2103
Figure 55. 16-Bit PPG Mode Operation Example104
16-Bit Timer 2 Block Diagram105
Register Map105
Figure 56. 16-Bit Timer 2 Block Diagram105
Table 19. TIMER 2 Register Map105
Register Description106
12 12-Bit ADC108
Conversion Timing108
Block Diagram109
Figure 57. 12-Bit ADC Block Diagram109
Figure 58. A/D Analog Input Pin with a Capacitor109
ADC Operation110
Figure 59. Control Registers and Align Bits110
Register Map111
Register Description111
Figure 60. ADC Operation Flow Sequence111
Table 20. ADC Register Map111
13 I2C114
Block Diagram114
Figure 61. I 2 C Block Diagram114
Bit Transfer115
Start/ Repeated Start/ Stop115
Figure 62. Bit Transfer on the I2C-Bus115
Figure 63. START and STOP Condition115
Data Transfer116
Acknowledge116
Figure 64. Data Transfer on the I2C-Bus116
Synchronization/ Arbitration117
Figure 65. Acknowledge on the I2C-Bus117
Figure 66. Clock Synchronization During Arbitration Procedure118
Figure 67. Arbitration Procedure of Two Masters118
Block Operation119
I2C Block Initialization Process119
I2C Interrupt Service120
Master Transmitter121
Slave Receiver123
Register Map124
Table 21. Register Map124
I2C Register Description125
14 Usart129
Block Diagram130
Figure 68. USART Block Diagram130
Clock Generation131
Figure 69. Clock Generation Block Diagram131
Table 22. Equations for Calculating Baud Rate Register Setting131
External Clock (XCK)132
Synchronous Mode Operation132
Figure 70. Synchronous Mode XCK Timing132
Data Format133
Figure 71. a Frame Format133
Parity Bit134
USART Transmitter134
Sending Tx Data134
Transmitter Flag and Interrupt134
Parity Generator135
Disabling Transmitter135
USART Receiver135
Receiving Rx Data135
Receiver Flag and Interrupt136
Parity Checker137
Disabling Receiver137
Asynchronous Data Reception137
Figure 72. Start Bit Sampling137
Figure 73. Sampling of Data and Parity Bit138
Figure 74. Stop Bit Sampling and Next Start Bit Sampling138
SPI Mode139
SPI Clock Formats and Timing139
Table 23. CPOL Functionality139
Figure 75. SPI Clock Formats When UCPHA = 0140
Figure 76. SPI Clock Formats When UCPHA = 1141
Receiver Time out (RTO)142
Figure 77. Example for RTO in USART142
Table 24. Example Condition of RTO142
Register Map143
Table 25. USART Register Map143
Register Description144
Baud Rate Settings (Example)151
Table 26. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies151
0% Error Baud Rate153
Figure 78. 0% Error Baud Rate Block Diagram153
15 Power down Operation154
Peripheral Operation in IDLE/ STOP Mode154
Table 27. Peripheral Operation Status During Power-Down Mode154
IDLE Mode155
STOP Mode155
Figure 79. IDLE Mode Release Timing by an External Interrupt155
Released Operation of STOP Mode156
Figure 80. STOP Mode Release Timing by External Interrupt156
Figure 81. STOP Mode Release Flow157
Register Map158
Register Description158
Table 28. Power-Down Operation Register Map158
16 Reset159
Reset Block Diagram159
Figure 82. Reset Block Diagram159
Table 29. Hardware Setting Values in Reset State159
Power on Reset160
Figure 83. Fast VDD Rising Time160
Figure 84. Internal RESET Release Timing on Power-Up160
Figure 85. Configuration Timing When Power-On161
Figure 86. Boot Process Waveform161
External RESETB Input162
Table 30. Boot Process Description162
Figure 87. Timing Diagram after RESET163
Figure 88. Oscillator Generating Waveform Example163
Low Voltage Reset Process164
Figure 89. Block Diagram of LVR164
Figure 90. Internal Reset at Power Fail Situation164
LVI Block Diagram165
Figure 91. Configuration Timing When LVR RESET165
Figure 92. LVI Block Diagram165
Register Map166
Reset Operation Register Description166
Table 31. Reset Operation Register Map166
17 Memory Programming168
Flash Control and Status Registers168
Register Map168
Table 32. Flash Control and Status Register Map168
Register Description169
Figure 93. Read Device Internal Checksum (Full Size)173
Figure 94. Read Device Internal Checksum (User Define Size)174
Table 33. Program and Erase Time175
Memory Map176
Flash Memory Map176
Figure 95. Flash Memory Map176
Figure 96. Address Configuration of Flash Memory176
Serial In-System Program Mode177
Flash Operation177
Figure 97. the Sequence of Page Program and Erase of Flash Memory177
Figure 98. the Sequence of Bulk Erase of Flash Memory178
Mode Entrance Method of ISP Mode182
Mode Entrance Method for ISP182
Figure 99. ISP Mode182
Table 34. Operation Mode182
Table 35. Mode Entrance Method for ISP182
Security183
Configure Option183
Table 36. Security Policy Using Lock Bits183
How to Write the Configure Option in User Program184
18 Development Tools185
Compiler185
Core and Debug Tool Information185
Table 37. Information of Core and Debug Emulation Interfaces185
Feature of 94/96/97 Series Core186
Table 38. Core and Debug Interface by Series186
Table 39. Feature Comparison Chart by Series and Cores186
OCD Type of 94/96/97 Series Core188
Table 40. OCD Type of each Series188
Table 41. Comparison of OCD 1 and OCD 2188
Interrupt Priority of 94/96/97 Series Core189
Table 42. Interrupt Priorities in Groups and Levels189
Extended Stack Pointer of 94/96/97 Series Core190
Figure 100. Configuration of the Extended Stack Pointer190
OCD (On-Chip Debugger) Emulator and Debugger191
Table 43. Debug Feature by Series191
Figure 101. OCD 1 and OCD 2 Connector Pin Diagram192
Table 44. OCD 1 and OCD 2 Pin Description192
On-Chip Debug System193
Figure 102. Debugger (OCD1/OCD2) and Pinouts193
Table 45. OCD Features193
Entering Debug Mode194
Figure 103. On-Chip Debugging System in Block Diagram194
Figure 104. Timing Diagram of Debug Mode Entry194
Two-Wire Communication Protocol195
Figure 105. 10-Bit Transmission Packet196
Figure 106. Data Transfer on OCD196
Figure 107. Bit Transfer on Serial Bus197
Figure 108. Start and Stop Condition197
Figure 109. Acknowledge on Serial Bus198
Figure 110. Clock Synchronization During Wait Procedure198
Programmers199
OCD Emulator199
Figure 111. E-PGM+ (Single Writer) and Pinouts199
Gang Programmer200
Flash Programming200
On-Board Programming200
Figure 112. E-Gang4 and E-Gang6 (for Mass Production)200
Table 46. Pins for Flash Programming200
Connection of Transmission201
Figure 113. Connection of Transmission201
Circuit Design Guide202
Figure 114. PCB Design Guide for On-Board Programming203
Appendix204
Instruction Table204
Table 47. Instruction Table204
Table 47. Instruction Table (Continued)205
Table 47. Instruction Table (Continued)206
Table 47. Instruction Table (Continued)207
Table 47. Instruction Table (Continued)208
Revision History209

Abov A96G174 - Connection of Transmission; Figure 113. Connection of Transmission

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