Abov MC96F6432Q User Manual

MC96F6432
June 22, 2018 Ver. 2.9 193
11.11.7 Register Description for ADC
ADCDRH (A/D Converter Data High Register) : 9FH
7
6
5
4
3
2
1
0
ADDM11
ADDM10
ADDM9
ADDM8
ADDM7
ADDL11
ADDM6
ADDL10
ADDM5
ADDL9
ADDM4
ADDL8
R
R
R
R
R
R
R
R
Initial value : xxH
ADDM[11:4]
MSB align, A/D Converter High Data (8-bit)
ADDL[11:8]
LSB align, A/D Converter High Data (4-bit)
ADCDRL (A/D Converter Data Low Register) : 9EH
7
6
5
4
3
2
1
0
ADDM3
ADDL7
ADDM2
ADDL6
ADDM1
ADDL5
ADDM0
ADDL4
ADDL3
ADDL2
ADDL1
ADDL0
R
R
R
R
R-
R
R
R
Initial value : xxH
ADDM[3:0]
MSB align, A/D Converter Low Data (4-bit)
ADDL[7:0]
LSB align, A/D Converter Low Data (8-bit)
ADCCRH (A/D Converter Control High Register) : 9DH
7
6
5
4
3
2
1
0
ADCIFR
–
TRIG2
TRIG1
TRIG0
ALIGN
CKSEL1
CKSEL0
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
ADCIFR
When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit,
write ‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has
no effect.
0
ADC Interrupt no generation
1
ADC Interrupt generation
TRIG[2:0]
A/D Trigger Signal Selection
TRIG2
TRIG1
TRIG0
Description
0
0
0
ADST
0
0
1
Timer 1 A match signal
0
1
0
Timer 4 overflow event signal
0
1
1
Timer 4 A match event signal
1
0
0
Timer 4 B match event signal
1
0
1
Timer 4 C match event signal
Other Values
Not used
ALIGN
A/D Converter data align selection.
0
MSB align (ADCDRH[7:0], ADCDRL[7:4])
1
LSB align (ADCRDH[3:0], ADCDRL[7:0])
CKSEL[1:0]
A/D Converter Clock selection
CKSEL1
CKSEL0
Description
0
0
fx/1
0
1
fx/2
1
0
fx/4
1
1
fx/8

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English