Abov MC96F6432Q User Manual

MC96F6432
June 22, 2018 Ver. 2.9 263
USI1CR1 (USI1 Control Register 1: For UART, SPI, and I2C mode) : E9H
7
6
5
4
3
2
1
0
USI1MS1
USI1MS0
USI1PM1
USI1PM0
USI1S2
USI1S1
ORD1
USI1S0
CPHA1
CPOL1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
USI1MS[1:0]
Selects operation mode of USI1
USI1MS1
USI1MS0
Operation mode
0
0
Asynchronous Mode (UART)
0
1
Synchronous Mode
1
0
I2C mode
1
1
SPI mode
USI1PM[1:0]
Selects parity generation and check methods (only UART mode)
USI1PM1
USI1PM0
Parity
0
0
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
USI1S[2:0]
When in asynchronous or synchronous mode of operation,
selects the length of data bits in frame
USI1S2
USI1S1
USI1S0
Data Length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
ORD1
This bit in the same bit position with USI1S1. The MSB of the data
byte is transmitted first when set to ‘1’ and the LSB when set to ‘0’
(only SPI mode)
0
LSB-first
1
MSB-first
CPHA1
This bit is in the same bit position with USI1S0. This bit determines if
data are sampled on the leading or trailing edge of SCK1 (only SPI
mode).
CPOL1
CPHA1
Leading edge
Trailing edge
0
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
Sample (Falling)
Setup (Rising)
1
1
Setup (Falling)
Sample (Rising)
CPOL1
This bit determines the clock polarity of ACK in synchronous or SPI
mode.
0
TXD change@Rising Edge, RXD change@Falling Edge
1
TXD change@Falling Edge, RXD change@Rising Edge

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English