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Abov MC96F6432Q User Manual

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MC96F6432
310 June 22, 2018 Ver. 2.9
The Byte erase program procedure in user program mode
1. Page buffer clear (FMCR=0x01)
2. Write 0 to page buffer
3. Set flash sector address register (FSADRH/FSADRM/FSADRL).
4. Set flash identification register (FIDR).
5. Check the UserID for to prevent the invalid work
(Note)
.
6. Set flash mode control register (FMCR).
7. Erase verify
Notes) 1. Please refer to the chapter “Protection for Invalid Erase/Write”.
2. On flash memory erase and write, it should be disabled the RXE0/1 bit of USI0CR2/USI1CR2
register.
Program Tip byte erase
MOV FMCR,#0x01 ;page buffer clear
NOP ;Dummy instruction, This instruction must be needed.
NOP ;Dummy instruction, This instruction must be needed.
NOP ;Dummy instruction, This instruction must be needed.
MOV A,#0
MOV DPH,#0x80 ;Page Buffer Address is 8000H
MOV DPL,#0
MOVX @DPTR,A
MOV DPH,#0x80
MOV DPL,#0x05
MOVX @DPTR,A ;Write ‘0’ to page buffer
MOV FSADRH,#SAH ;Sector Address High Byte
MOV FSADRM,#SAM ;Sector Address Middle Byte
MOV FSADRL,#SAL ;Sector Address Low Byte
MOV FIDR,#0xA5 ;Identification value
MOV A,#ID_DATA_1 ;Check the UserID(written by user)
CJNE A,UserID1,No_WriteErase ;This routine for UserID must be needed.
MOV A,#ID_DATA_2
CJNE A,UserID2,No_WriteErase
MOV FMCR,#0x02 ;Start flash erase mode
NOP ;Dummy instruction, This instruction must be needed.
NOP ;Dummy instruction, This instruction must be needed.
NOP ;Dummy instruction, This instruction must be needed.
LJMP Erase_verify
---
No_WriteErase:
MOV FIDR,#00H
MOV UserID1,#00H
MOV UserID2,#00H
---
Erase_verify:
---
Verify_error:
---

Table of Contents

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Abov MC96F6432Q Specifications

General IconGeneral
Core8051
Flash Memory64 KB
PackageLQFP-48
PWMYes
UART1
SPI1
I2C1
CPU Speed16 MHz
GPIO Pins36
Operating Voltage2.4V to 5.5V
Timers3
Operating Temperature-40°C to 85°C
ADC12-bit, 8 channels

Summary

Block Diagram

Pin Assignment

Pin Description

Electrical Characteristics

Absolute Maximum Ratings

Specifies the absolute maximum ratings for the device, beyond which permanent damage may occur.

Recommended Operating Conditions

Outlines the recommended operating voltage and temperature ranges for reliable device performance.

DC Characteristics

Provides DC electrical characteristics including input/output voltage levels, leakage current, and pull-up resistor values.

Memory

SFR Map

I/O Ports

Interrupt Controller

Interrupt Vector Table

Provides the table of interrupt sources, their symbols, enable bits, priorities, and vector addresses.

Peripheral Hardware

Clock Generator

Describes the clock generator, its overview, block diagram, and register map for system clock control.

Basic Interval Timer

Explains the 8-bit basic interval timer, its features, block diagram, and register descriptions.

Watch Dog Timer

Details the watchdog timer, its overview, timing waveform, block diagram, and register descriptions.

Timer 0

Covers Timer 0 overview, operating modes, 8-bit timer/counter mode, PWM mode, and capture mode.

Timer 1

Explains Timer 1 overview, operating modes, 16-bit timer/counter, capture, and PPG modes.

Timer 2

Details Timer 2 overview, operating modes, 16-bit timer/counter, capture, and PPG modes.

Timer 3, 4

Describes Timer 3 and 4 overview, operating modes including 8-bit and 16-bit timer/counter, capture, and PWM modes.

SPI 2

Details the SPI 2 interface, its overview, block diagram, data transfer, SS2 pin function, and timing diagrams.

12-Bit A/D Converter

Covers the 12-bit A/D converter overview, conversion timing, block diagram, ADC operation, and registers.

USI0 (UART + SPI + I2C)

Explains the USI0 module, its overview, UART mode, SPI mode, and I2C mode operations.

USI1 (UART + SPI + I2C)

Details the USI1 module, its overview, UART mode, SPI mode, and I2C mode operations.

Power Down Operation

Overview

Introduces the power-down modes (Main-IDLE, Sub-IDLE, STOP) for minimizing power consumption.

RESET

Reset Source

Lists the five types of reset sources available for the MC96F6432.

On-chip Debug System

Flash Memory

Protection for Invalid Erase/Write

Describes methods to protect flash memory from invalid erase/write operations.

Configure Option

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