7451A/7461A/7461P Digital Multimeter Operation Manual
6.7.5 Status Register Structure
6-51
4. Standard event status register
Allocation in the standard event register is shown in Table 6-8.
Conditions which clear the standard event status register
• When the power is turned on.
• When the *CLS command is executed.
• When the *ESR? command is executed..
Conditions which clear the standard event status enable register
• When the power is turned on. (When the PSC flag is set to 1)
• When the *ESE0 command is executed.
Table 6-8 Standard Event Status Register (SESR)
bit Name Description
0OPC
Operation Complete
ON: This bit is set to 1 when all operations are complete after receiving the *OPC
command.
1 Not used Always 0
2 QYE
Query Error
ON: This bit is set to 1 under any of the following conditions.
• When the data is read, but no data exists in the output buffer and no data to be
output exists.
• When data in the output buffer is lost.
3 DDE
Device Dependent
Error
ON: This bit is set to 1 when the error, which depends on the device, occurs.
4EXE
Execution Error
ON: This bit is set to 1 when the received command cannot be executed.
This bit is set to 1 when the command parameter contains an error.
5CME
Command Error
ON: This bit is set to 1 when the received command spelling is incorrect.
6 Not used Always 0
7PON
Power On
ON: This bit is set to 1 when the power is turned on.
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