ADCMT 7461A User Manual

7451A/7461A/7461P Digital Multimeter Operation Manual
6.7.5 Status Register Structure
6-52
5. Measurement event register
Allocation in the measurement event register is shown in Table 6-9.
Conditions which clear the measurement event register
• When the power is turned on.
• When the *CLS command is executed.
• When the :STATus:MEASurement[:EVENt]?" command is executed.
• When the MSR? command is executed.
Conditions which clear the measurement event enable register
• When the power is turned on.
• When the :STATus:MEASurement:ENABle 0 command is executed.
• When the MSE0 command is executed.
Table 6-9 Measurement Event Register (MER)
bit Name Description
0FL
FAIL
ON: This bit is set to 1 when the comparator calculation result satisfies the FAIL
conditions.
1PS
PASS
ON: This bit is set to 1 when the comparator calculation result satisfies the PASS
conditions.
2 Not used Always 0
3 Not used Always 0
4 Not used Always 0
5 Not used Always 0
6 Not used Always 0
7 Not used Always 0
8EOM
End of measure
ON: This bit is set to 1 when the measurement is complete.
9EOS
End of store
ON: This bit is set to 1 when no more measurement data can be stored in the mea-
surement memory.
10 SM
Smoothing complete
ON: This bit is set to 1 when the smoothing count reaches the specified number.
11 STAT
Statistics complete
ON: This bit is set to 1 when the statistical processing is complete.
12 Not used Always 0
13 ELD
End of Level/Delta
ON: This bit is set to 1 when all measurements are complete after the LEVEL
trigger or DELTA trigger is detected.
14 LDD
Level/Delta Detected
ON: This bit is set to 1 when the LEVEL trigger or DELTA trigger is detected.
15 Not used Always 0

ADCMT 7461A Specifications

General

Brand	ADCMT
Model	7461A
Category	Multimeter
Language	English