ADLINK Technology VPX3-TL BIOS - Page 13

13
VPX3-TL BIOS
BIOS Item Options Description
MSR 1FC bit 20)
Intel(R) Speed Shift
Technology
Enabled
Disabled
Enable/Disable Intel(R) Speed Shift
Technology support. Enabling will expose
the CPPC v2 interface to allow for
hardware controlled P-states.
Per Core P State OS
control mode
Enabled
Disabled
Enable/Disable Per Core P state OS control
mode. Disabling will set Bit 31 = 1
command 0x06. When set, the highest
core request is used for all other core
requests.
HwP Autonomous Per
Core P State
Enabled
Disabled
Disable Autonomous PCPS (Bit 30 = 1,
command 0x11) Autonomous will request
the same value for all cores all the time.
Enable PCPS (default Bit 30 = 0, command
0x11)
HwP Autonomous EPP
Grouping
Enabled
Disabled
Enable EPP grouping (default Bit 29 =0,
command 0x11) Autonomous will request
the same values for all cores with same
EPP. Disable EPP grouping (Bit 29 =1 ,
command 0x11) autonomous will not
necessarily request same values for all
cores with same EPP.
EPB override over PECI Enabled
Disabled
Enable/Disable EPB override over PECI.
Enable by sending pcode command 0x2b ,
subcommand 0x3 to 1. This will allow OOB
EPB PECI override control
HwP Fast MSR Support Enabled
Disabled
Enable/Disable HwP Fast MSR Support for
IA32_HWP_REQUEST MSR.
HDC Control Enabled
Disabled
This option allows HDC configuration.
Turbo Mode Enabled
Disabled
Enable/Disable Per Core P state OS control
mode. Disabling will set Bit 31 = 1
command 0x06. When set, the highest
core request is used for all other core
requests.
View/Configure Turbo
Options
Submenu
Config TDP Configurations Submenu
CPU VR Settings Submenu
Platform PL1 Enable Enabled
Disabled
Enable/Disable Platform Power Limit 1
programming. If this option is enabled, it
activates the PL1 value to be used by the
processor to limit the average power of
given time window.