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Chapter 8: Theory of Operation
control refresh of the RAM array and can perform a search of stored data.
Master/Expander Connectors. Connectors J10 through J15 route state and
timing clocks, calibration signals, data search signals, and control from the Master
card to all cards in the module.
Connectors J20 through J23 route pattern recognition signals between all cards
in a card set as well as control clocks from the Master card to other cards in the
set.
Mainframe Interface and Control FPGA. The Mainframe interface consists
of an FPGA and the Mainframe Interface Connector. The connector brings power
onto the card and provides for control of the card by the analyzer mainframe. It
also provides a path for unloading acquired data to the analyzer display.
The FPGA converts bus signals generated by the mainframe processor into
control signals for the logic analyzer card. It also provides centralized functions
for the card such as I2C, Calibration signals, Flag routing, and Timing mode
sample clock.
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