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Chapter 3: Testing Logic Analyzer Performance
Test Pod 1 in 600 Mb/s Mode
tab. In the “State Mode Controls” section, select the “600 Mb/s / xxM
State” mode. (“xxM” indicates the module’s memory depth.) The mode
will change to 600 Mb/s and the clock setup will change to J clock, Rising
Edge. Do not change it to “Both Edges” yet.
9 In the logic analyzer’s Setup and Trigger window, Format tab, unassign all
pod 4 bits.
10 Assign bits 2, 6, 10, and 14 of Pod 1.
11 Ensure that the Pod 1 threshold is set to 1 volt. See page 66.
12 Use the scroll bar at the bottom of the window to scroll to the left and
select the “Clock thresh...” button. In the Clock Thresholds window,
ensure that the J clock threshold is set to Differential.
a Select Close to close the Clock Thresholds window.
13 Re-establish the trigger function:
a In the logic analyzer’s Setup and Trigger window, select the Trigger tab,
and the Trigger Functions subtab.
b Select “Find pattern n times” and select the “Replace” button.
c Enter “A” in the “Label 1 = “ field.
Determine and set Eye Finder Position (600 Mb/s mode)
14 In the Eye Finder (Sampling Positions) window, expand “Label1 (4
channels)”.
15 If the blue bars are not vertically aligned, align them. See page 68.
16 Grab the blue bar for “Label1 (4 Channels)” and move it to approximately
-2.9 ns. All blue bars will follow.
17 Run Eye Finder and note the average sampling position chosen by Eye
Finder:______ns. In the following example, the average sampling position
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