Interface Configuration
7750 SR Interface Configuration Guide Page 55
FRF.12 UNI/NNI Link Fragmentation
The user enables FRF.12 UNI/NNI link fragmentation on a per FR circuit basis. All FR SAPs
configured on this circuit are subject to fragmentation. A fragmentation header is added on top of
the standard Q.922 header. This header consists of 2 bytes containing the beginning bit (B-bit), the
End-bit (E-bit), the Control bit (C-bit), and the sequence number field. The fragmentation header
is included on frames of all SAPs regardless if the frame size is larger or not than the fragment
size.
The FECN, BECN, and DE bits of all fragments of a given FR frame are set to the same value as
the original frame. The FECN, BECN, and DE bits of a re-assembled frame are set to the logical
OR of the corresponding bits on the constituent fragments.
The operator must delete all configured FR SAPs on a port before enabling or disabling FRF.12
UNI/NNI on that port. Also, the user must shut down the port in order to change the value of the
fragmentation threshold.
A FR SAP on a FR circuit with FRF.12 UNI/NNI fragmentation enabled can be part of a VLL,
VPLS, IES, or VPRN service.
QoS for a link with FRF.12 UNI/NNI fragmentation is the same as for a MLFR bundle. The FR
class queue parameters and its scheduling parameters are configured by applying an egress QoS
profile to an FRF.12 UNI/NNI port. The FR scheduling class ingress re-assembly timeout is not
applicable to a FRF.12 UNI/NNI port.
MLFR/FRF.12 Support of APS, BFD, and Mirroring Features
The following APS support is provided:
• Single-chassis APS is supported on a SONET/SDH port with FRF.12 UNI/NNI
fragmentation enabled on the port or on a constituent TDM circuit.
• Single-chassis APS is supported on a SONET/SDH port with FRF.12 e2e fragmentation
enabled on one or more FR SAPs on the port or on a constituent TDM circuit.
• Single-chassis APS is not supported on a SONET/SDH port with MLFR bundles
configured.
• Multi-chassis APS is not supported on a SONET/SDH port with FR encapsulation
configured on the port or on a constituent TDM circuit.
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