Alinx AX7021 - Page 15

ZYNQ FPGA Development Board AX7021 User Manual
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DDR3 DRAM Pin Assignment
Signal Name
ZYNQ Pin Name
Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C2
DDR3_DQS0_N
PS_DDR_DQS_N0_502
D2
DDR3_DQS1_P
PS_DDR_DQS_P1_502
H2
DDR3_DQS1_N
PS_DDR_DQS_N1_502
J2
DDR3_DQS2_P
PS_DDR_DQS_P2_502
N2
DDR3_DQS2_N
PS_DDR_DQS_N2_502
P2
DDR3_DQS3_P
PS_DDR_DQS_P3_502
V2
DDR3_DQS4_N
PS_DDR_DQS_N3_502
W2
DDR3_D0
PS_DDR_DQ0_502
D1
DDR3_D1
PS_DDR_DQ1_502
C3
DDR3_D2
PS_DDR_DQ2_502
B2
DDR3_D3
PS_DDR_DQ3_502
D3
DDR3_D4
PS_DDR_DQ4_502
E3
DDR3_D5
PS_DDR_DQ5_502
E1
DDR3_D6
PS_DDR_DQ6_502
F2
DDR3_D7
PS_DDR_DQ7_502
F1
DDR3_D8
PS_DDR_DQ8_502
G2
DDR3_D9
PS_DDR_DQ9_502
G1
DDR3_D10
PS_DDR_DQ10_502
L1
DDR3_D11
PS_DDR_DQ11_502
L2
DDR3_D12
PS_DDR_DQ12_502
L3
DDR3_D13
PS_DDR_DQ13_502
K1
DDR3_D14
PS_DDR_DQ14_502
J1
DDR3_D15
PS_DDR_DQ15_502
K3
DDR3_D16
PS_DDR_DQ16_502
M1
DDR3_D17
PS_DDR_DQ17_502
T3
DDR3_D18
PS_DDR_DQ18_502
N3
DDR3_D19
PS_DDR_DQ19_502
T1
DDR3_D20
PS_DDR_DQ20_502
R3
DDR3_D21
PS_DDR_DQ21_502
T2
DDR3_D22
PS_DDR_DQ22_502
M2
DDR3_D23
PS_DDR_DQ23_502
R1
DDR3_D24
PS_DDR_DQ24_502
AA3
DDR3_D25
PS_DDR_DQ25_502
U1
DDR3_D26
PS_DDR_DQ26_502
AA1
DDR3_D27
PS_DDR_DQ27_502
U2
DDR3_D28
PS_DDR_DQ28_502
W1
DDR3_D29
PS_DDR_DQ29_502
Y3
DDR3_D30
PS_DDR_DQ30_502
W3
DDR3_D31
PS_DDR_DQ31_502
Y1
DDR3_DM0
PS_DDR_DM0_502
B1
DDR3_DM1
PS_DDR_DM1_502
H3
DDR3_DM2
PS_DDR_DM2_502
P1
DDR3_DM3
PS_DDR_DM3_502
AA2
DDR3_A0
PS_DDR_A0_502
M4
DDR3_A1
PS_DDR_A1_502
M5
DDR3_A2
PS_DDR_A2_502
K4
DDR3_A3
PS_DDR_A3_502
L4
DDR3_A4
PS_DDR_A4_502
K6
DDR3_A5
PS_DDR_A5_502
K5
DDR3_A6
PS_DDR_A6_502
J7
DDR3_A7
PS_DDR_A7_502
J6
DDR3_A8
PS_DDR_A8_502
J5