Alinx AX7021 - Page 43

ZYNQ FPGA Development Board AX7021 User Manual
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Figure3-4-2: The HDMI Interface on the Carrier Board
HDMI out Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
9134_CLK
B35_L4_N
G16
clock
9134_HS
B35_L21_P
E19
line synchronization
9134_VS
B35_L1_P
F16
column synchronization
9134_DE
B35_L21_N
E20
Signal valid
9134_D[0]
B35_L24_P
H22
Data0
9134_D[1]
B35_L24_N
G22
Data 1
9134_D[2]
B35_L6_P
G17
Data 2
9134_D[3]
B35_L6_N
F17
Data 3
9134_D[4]
B35_L4_P
G15
Data 4
9134_D[5]
B35_L3_N
D15
Data 5
9134_D[6]
B35_L3_P
E15
Data 6
9134_D[7]
B35_L5_P
F18
Data 7
9134_D[8]
B35_L5_N
E18
Data 8
9134_D[9]
B35_IO0
H17
Data 9
9134_D[10]
B35_IO25
H18
Data 10
9134_D[11]
B35_L19_P
H19
Data 11
9134_D[12]
B35_L19_N
H20
Data 12
9134_D[13]
B35_L20_P
G19
Data 13
9134_D[14]
B35_L20_N
F19
Data 14
9134_D[15]
B35_L22_P
G20
Data 15
9134_D[16]
B35_L22_N
G21
Data 16
9134_D[17]
B35_L23_P
F21
Data 17
9134_D[18]
B35_L23_N
F22
Data 18
9134_D[19]
B35_L17_P
E21
Data 19
9134_D[20]
B35_L17_N
D21
Data 20
9134_D[21]
B35_L16_P
D22
Data 21
9134_D[22]
B35_L16_N
C22
Data 22
9134_D[23]
B35_L18_P
B21
Data 23
9134_SCK
B35_L13_P
B19
Audio Interface I2S Clock
9134_SPDIF
B35_L1_N
E16
Audio S/PDIF input
9134_MCLK
B35_L2_P
D16
Audio input master clock
9134_WS
B35_L14_N
C20
Audio interface I2S word
selection
9134_SD0
B35_L14_P
D20
Audio Interface I2S Data0
9134_SD1
B35_L12_P
D18
Audio Interface I2S Data1
9134_SD2
B35_L12_N
C19
Audio Interface I2S Data2