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Allen-Bradley ControlLogix 1756 - Page 65

Allen-Bradley ControlLogix 1756
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Publication 1756-RM084F-EN-P - July 2002
Entering Ladder Diagram Logic 4-5
ARL
ARL(
channel,destination,serial_port_control,string_length,
characters_read
);
ASN
ASN(
source,destination
);
ATN
ATN(
source,destination
);
AVE
AVE(
array,dim_to_vary,destination,control,length,position
);
AWA
AWA(
channel,source,serial_port_control,string_length,characters_sent
);
AWT
AWT(
channel,source,serial_port_control,string_length,characters_sent
);
BRK
BRK();
BSL
BSL(
array,control,source_bit,length
);
BSR
BSR(
array,control,source_bit,length
);
BTD
BTD(
source,source_bit,destination,destination_bit,length
);
CLR
CLR(
destination
);
CMP
CMP(
expression
);
CONCAT
CONCAT(
sourceA,sourceB,destination
)
COP
COP(
source,destination,length
);
COS
COS(
source,destination
);
CPS
CPS(
source,destination,length
)
CPT
CPT(
destination
,
expression
);
CTD
CTD(
counter,preset,accum
);
CTU
CTU(
counter,preset,accum
);
DDT
DDT(
source,reference,result,cmp_control,length,position,result_control,
length,position
);
DEG
DEG(
source,destination
);
DELETE
DELETE(
source,quantity,start,destination
);
DIV
DIV(
source_A,source_B,destination
);
DTOS
DTOS(
source,destination
);
DTR
DTR(
source,mask,reference
);
EOT
EOT(
data_bit
);
EQU
EQU(
source_A,source_B
);
FAL
FAL(
control,length,position,mode,destination,expression
);
FBC
FBC(
source,reference,result,cmp_control,length,position,result_control,
length,position
);
FFL
FFL(
source,FIFO,control,length,position
);
FFU
FFU(
FIFO,destination,control,length,position
);
FIND
FIND(
source,search,start,result
);
FLL
FLL(
source,destination,length
);
FOR
FOR(
routine_name,index,initial_value,terminal_value,step_size
);
FRD
FRD(
source,destination
);
Instruction: Neutral text format:
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