AMLOGIC S905D3 - Page 42

0.6 (2019–07–25)
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Signal Name Type Description
TDMB_D5 DIO Data input/output 5 of TDM port B
TDMB_D6 DIO Data input/output 6 of TDM port B
TDMB_D7 DIO Data input/output 7 of TDM port B
TDMB_SCLK DO Bit clock output of TDM port B
TDMB_FS DO Frame sync output of TDM port B (Word clock of I2S)
TDMB_SLV_SCLK DI Bit clock input of TDM port B
TDMB_SLV_FS DI Frame sync input of TDM port B (Word clock of I2S)
TDMC_DIN0 DI Data input 0 of TDM port C
TDMC_DIN1 DI Data input 1 of TDM port C
TDMC_DIN2 DI Data input 2 of TDM port C
TDMC_DIN3 DI Data input 3 of TDM port C
TDMC_D0 DIO Data input/output 0 of TDM port C
TDMC_D1 DIO Data input/output 1 of TDM port C
TDMC_D2 DIO Data input/output 2 of TDM port C
TDMC_D3 DIO Data input/output 3 of TDM port C
TDMC_D4 DIO Data input/output 4 of TDM port C
TDMC_D5 DIO Data input/output 5 of TDM port C
TDMC_SCLK DO Bit clock output of TDM port C
TDMC_FS DO Frame sync output of TDM port C (Word clock of I2S)
TDMC_SLV_SCLK DI Bit clock input of TDM port C
TDMC_SLV_FS DI Frame sync input of TDM port C (Word clock of I2S)
Table 4-28 PDM Signal Description
Signal Name Type Description
PDM_DIN0 DI PDM input data 0 signal
PDM_DIN1 DI PDM input data 1 signal
PDM_DIN2 DI PDM input data 2 signal
PDM_DIN3 DI PDM input data 3 signal
PDM_DCLK DO PDM output clock signal
Table 4-29 JTAG Interface Signal Description
Signal Name Type Description
JTAG_A_TDO DO JTAG data output channel A
JTAG_A _TDI DI JTAG data input channel A
JTAG_A_TMS DI JTAG Test mode select input channel A
JTAG_A_CLK DI JTAG Test clock input channel A
S905D3 Quick Reference Manual 4 Pinout Specification
Preliminary Version
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