ARM Cortex-M3 DesignStart User Manual

• Peripherals for:
— Application use, including Timers, UART, Watchdog, Real Time Clock (RTC), True Random
Number Generator (TRNG).
— MPS2+ platform, including Color LCD, Audio, and Ethernet.
— Arduino Shield expansion using the adapter for the Arduino board.
• SPI interface supporting application persistent storage on microSD card.
• Reusable ARM Advanced Microcontroller Bus Architecture (AMBA) SoC interconnect components
for system level development.
You must not modify the obfuscated Cortex-M3 processor (cortexm3ds_logic.v).
You are only permitted to redistribute the following files (modified or original), with the original headers
unchanged, and any modifications clearly identified:
• fpga_top.v
• m3ds_user_partition.v
• m3ds_peripherals_wrapper.v
1.1.2 Execution Testbench
The Execution Testbench in Cortex-M3 DesignStart Eval is an RTL package that allows system design
and simulation with a suitable Verilog simulator.
The Cortex-M3 DesignStart Eval Execution Testbench includes:
• A simulation model of the processor that includes register visibility and instruction execution tracing.
• Memory models that match the FPGA target.
• ARM CoreSight
™
debug test engine that is preconfigured for a single fixed debug and trace
implementation.
• Integration tests for memories and internal peripherals.
You are expected to modify the test code to support any modifications you make to your design. You
must not redistribute any test code or binaries from these deliverables unless it is developed using mbed
source code.
You are only permitted to redistribute the following files (modified or original), with the original headers
unchanged, and any modifications clearly identified:
• tb_fpga_shield.v
• cmsdk_uart_capture_ard.v
1.1.3 FPGA Evaluation Flow
The Cortex-M3 DesignStart Eval FPGA Evaluation Flow allows developers to build an image file of the
simulation system that can be used with the ARM Versatile Express Cortex-M Prototyping System
(V2M-MPS2+). The FPGA image can be customized to the user system requirements.
The Cortex-M3 DesignStart Eval FPGA Evaluation Flow requires the purchase of the MPS2+ FPGA
platform.
The MPS2+ FPGA platform includes a Motherboard Configuration Controller (MCC) on the baseboard,
which provides the following features that are necessary to emulate an ARM mbed compliant system:
• Target application code. The target has no flash memory. The SRAM is instead initialized at powerup
by the MCC using information stored on the configuration microSD card.
• DAPLink implementing CMSIS-DAP over USB for debug access.
• UART access is provided by a serial connector (and included serial to USB cable).
• Real Time Clock (RTC) initialization from baseboard processor on powerup.
For more information on how to use the MPS2+ FPGA platform, see the ARM
®
Versatile
™
Express
Cortex
®
-M Prototyping System (V2M-MPS2 and V2M-MPS2+) Technical Reference Manual.
You must not redistribute any FPGA bit files or other representations of the design that are produced
from Cortex-M3 DesignStart Eval.
1 Introduction
1.1 About Cortex
®
-M3 DesignStart
™
Eval
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 1-13
Non-Confidential

ARM Cortex-M3 DesignStart Specifications

General

Brand	ARM
Model	Cortex-M3 DesignStart
Category	Motherboard
Language	English