Cray CRAY-1 - Page 178

I
DV module
The input channel control logic for the DV module differs from that for
the
OJ module in six respects.
1. When a parity error is detected, the condition is noted and saved
but the
Channel Error Flag (CE) is not set until the Input Dis-
connect pulse
arrives. This change prevents an error interrupt
request from occurring and no data is lost. The only interrupt
request that occurs in this situation is the normal one at dis-
connect time, even though the Channel Error Flag is set at this
time to indicate the parity fault condition.
2. For the DV module, the input channel is not forced active by the
Clear I/O signal. If, however, the channel is already active, it
remains active.
3. In an Input Ready pulse is received while the input channel is not
active, even if (CA) = (CL), the ready.is held until the channel
goes
active or until a Master Clear is received, (i.e., a Clear
I/O signal is generated by the MCU or a Programmed I/O Master
Clear sequence is performed). No error interrupt request is made.
4. If the channel address (CA) equals the limit address (CL) and the
input channel
is active, an interrupt request is generated and the
input channel goes
inactive without receiving an Input Disconnect
pulse.
When the Disconnect pulse is received after (CA) = (CL),
it is ignored since the interrupt request has already been generated.
5.
The only
conditions
that cause the Channel
Error (CE) flag
to
set are:
a.
Input Ready and
Reference; double
Ready condition
b.
Input
Ready and
Active and (CA) =
(CL); double Ready condition
c.
Parity Fault Flag set and
Disconnect
d.
Parity Fault Flag set and Active and (CA) = (CL)
6.
The Clear I/O signal clears the Parity Fault flag.
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