Cray CRAY-1 - Page 199

SUMMARY OF TIMING INFORMATION
A
When issue conditions are satisfied an instruction completes in a fixed
amount of time. Instruction issue may cause reservations to be placed
on a functional unit or registers. Knowledge of the issue conditions,
instruction execution times and reservations permit accurate timing of
code sequences. Memory bank conflicts due to I/O activity are the only
element
of unpredictability.
SCALAR INSTRUCTIONS
Four conditions must be satisfied for issue of a scalar instruction:
1. The functional unit must be free. No conflicts can arise with other
scalar instructions; however, vector floating point instructions
reserve the
floating point units. Memory references may be delayed
due to conflicts.
2. The result register must be free.
3. The operand register must be free.
4. Issue is delayed 1 clock period if a result register group input path
conflict would exist with a previously issued instruction. One input
path
exists for each of the four register groups (A, B, Sand T).
Scalar instructions place reservations only on result registers. A result
register is reserved for the execution time of the instruction. No
reservations are placed on the functional unit or operand registers.
I A transmit vector mask to Si (073) instruction is delayed by (VL) + 6
clock periods
from the issue of a previous vector mask (175) instruction
and is delayed by 6 clock periods from the issue of a preceding transmit
(Sj) to VM (003) instruction.
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