Cray CRAY-1 - Page 200

Execution times in clock periods are given below.
(A=A register, M=Hemory, B=B register, S=S register, I=Immediate, C=ChannelJ
24-bit results:
A-+-M
M-+-A
A--+-B
B~A
A~S
A-+- I
64-bit results:
S~M
M~S
S --+-T
T~S
S --+- I
S ~S(log.)S
S ~S(shift)I
S ~S(shift)A
S --+- S ( ma s k ) I
RTC --+- S
11*
1*
1
1
1
1
11*
1*
1
1
1
1
2
3
1
1
A~C
4
A--+- A+A
2
A--+- AxA
6
A--+- pop(S)
4
A--+-lzc(S)
3
VL~A
1
S --+- S+S
3
S~S(f.add)S
6*
S ~S( f .mul t)S
7*
S--+-S(r.a.)
14*
S~V
5
V--+-S
3
S --+- VM
1
S --+- RTC
1
S--+-A
2
VM --+- S
3
* Issue may be delayed because of a functional unit reservation by a
vector
instruction. Memory may be considered a functional unit for
timing considerations.
VECTOR INSTRUCTIONS
Four conditions must be satisfied for issue of a vector instruction:
1. The functional unit must be free. (Conflicts may occur with vector
operations.)
2. The result register must be free. (Conflicts may occur with vector
operations.)
3. The operand registers must be free or at chain slot time.
4.
Memory must be quiet if the instruction references memory.
Vector instructions place reservations on functional units and registers
for the duration of execution.
1. Functional units are reserved
for VL+4 clock periods. Memory is
reserved for VL+5 clock periods on a write operation, VL+4 clock
periods
on a read operation.
2240004
A-2
E