Cray CRAY-1 - Page 203

Scalar instruction timing (no conflict):
CP n
Issue, reserve
register
CP
n+1
Address rank A, sense conflict
CP
n+2
Address
rank B
CP
n+3
Address
rank
C
CP n+9 Clear register reservation
CP n+10 Issue
HOLD ISSUE
A delay of issue results if a 100 - 137 instruction is in the NIP register
and a hold memory condition exists. The delay will depend on the hold
memory delay.
A delay
of issue results if a 100 - 137 instruction is in the NIP register
and a 100 - 137 instruction in process senses a conflict with rank A, B,
or C.
An additional 1 CP delay is added to a hold memory condition if a 070
I instruction destination register conflict is sensed.
2240004
A-5
E