Cray CRAY-1 - Page 202

Memory must be quiet before issue of the Band T register block copy
instructions (034-037). Subsequent instructions may not issue for 14+ (Ai)
clock periods
if (Ai),0 and 5 clock periods if (Ai)=O when reading
data to the Band T
registers (034,036). They may not issue for 6+(Ai)
clock periods
when storing data (035,037).
The Band T register block read (034,036) instructions require that there
be no register reservation on the A and S registers, respectively, before
issue.
Branch instructions cannot issue until an AO or SO operand register has
been free for one clock period. Fall-through in buffer requires two
clock periods. Branch-in-buffer requires five clock periods. When an
"out of buffer" condition occurs the execution time for a branch
instruction is 14 clock periods;
A two parcel instruction takes two clock periods to issue.
Instruction issue
is delayed 2 clock periods when the next instruction
parcel is in a different instruction parcel buffer. Instruction issue is
delayed 14 clock periods if the next instruction parcel is not in an
instruction parcel buffer.
HOLD MEMORY
A delay of 1, 2, or 3 CP will be added to a scalar memory read if a bank
conflict occurs with rank C, B, or A, respectively, of the memory access
network. A
conflict occurs if the address is in the same bank as the
address in rank
C, B, or A. Conflicts can occur only with scalar or I/O
references. The scalar instruction senses the conflict condition at
issue time + 1 CPo The scalar instruction address enters rank A of the
memory access network at issue time + 1 CPo The scalar instruction
address enters rank B at issue + 2 CPo The scalar instruction address
enters rank C
at issue + 3 CPo
t 18 clock periods for 8-bank phasing option; refer to section 5.
2240004
A-4
E