Cray CRAY-1 - Page 206

Alpha No. Alpha No,
Code
Aeelication
Used
Code
Ae~11cat1on
Used
M SERIES MODULES
T SERIES MODULES
MA
First
level product
24
TC
Clock fanout
9
MB
Second level product
10
I
TO Master clock
1
MC
Third level product
8
TX**
16-bank phasing
2
MD
Fourth level product
3
TV**
8-bank phasing
ME
Fifth level product
I
TZ Master clock fanout
MF
First level ends
2
V SERIES MODULES
MG
First section exponents
MH
Last section exponents
VA Data
to vector registers
32
VB
Vector data to jk functions
32
R SERIES MODULES
VC
Vector data to j functions
16
RA
Table for Ao
VD
Vector length control
1
RB
Table for Ao2
VE
Vector write control
RC
Form Al
VF
Front half vector shift
RD
Form Al
VG
Back half vector shift
RE
Form Al
VH
Front half vector add
4
RF
Form Al
2
VI
Back half vector add
2
RG
Form Al
VJ
Vector logical data
4
RH
FOnT! A 2
VK
Vector logical control
1
RI
Form A12
VL
Vector Pop Count Option
It
RJ FOnT! A12
VR
Vector registers
32
RK
Form A/
Form A12
Z SERIES MODULES***
RL
RM
Form A2
10
ZB
Storage w/memory data buffers
288
RN
FOnT! A2
ZC
Storage with clock fanout
36
RO
FOnT! A2
ZD
Storage R/W control
RP
Form A2
ZE
Storage section control
RQ
FOnT! A2
ZF
Storage with address fanout 120
RR
FOnT! A2
ZG Check bit generation
2
RS Reciprocal
coefficient
ZI
Corrective storage
RT Reciprocal coefficient
2
ZK
Syndrome generation and error
RU Operand delay
9
correction
32
RV Result exponent
I
ZV
Storage module 120
ZZ
Storage module w/address fan-
S
SERIES MODULES
out 588
SH*
16-bit synchronous
input data assembly
SI*
16-bit synchronous
output data assembly
I
*
One SH, SI module
pair interfaces to each eRI
disk controller. The
number depends on the system configuration.
**
For 8-bank phasing, TY modules are
substituted
for TX modules.
***
Figures are for 16-bank memory.
I
t
Included when Vector Population
Count Option
is
present.
2240004
B-2
E