78
Pin Pin Name Symbol
TOLERANT
Nch I/O Type Pullup LvCnv STBY stop Function
17 SCK2/PG6 SB_MUTE - - O - - - O/L O/L Surround Back Mute control pin
18 TEST1 TEST1 - - - - - - - - OPEN
19 INT5/PF7 REMOTE_IN - - I - - - I O/L REMOTE input pin
20 TXD0/PE0 TXD0 - - O - M3VPu - O/L O/L UPDATE TX pin
21 RXD0/PE1 RXD0 - - I - M3VPu - I O/L UPDATE RX pin
22 CTS0/SCLK0/PE2 SUB MUTE - - O - - - O/L O/L Sub Woofer MUTE pin
23 TXD1/PE4 HDMI_TX - - O - - - O/L O/L HDMI DEBUG TX pin
24 RXD1/PE5 HDMI_RX - - I - - - I O/L HDMI DEBUG RX pin
25 CST1/SCLK1/PE6 HDMIOST_MISO - - O - - - O/L O/L DATA output pin for HDMI OST
26 SDA0/SO0/PG0 INT_TX - - I - +3VHPu - I O/L HDMI INT TX interrupt
27 SCL0/SI0/PG1 CVBS_SW2 - - O - - - O/L O/L CVBS(Video) SW2 control pin
28 SCK0/PG2 HDMIOST_CLK - - O - - - O/L O/L Clock pin for HDMI OST
29 PB3 HDMI_RST - - O - - - O/L O/L HDMI Reset control pin
30 BOOT/TB0IN0/PH0 /BOOT - - I - M3VPu - I O/L Update Boot (At Update: Low)
31 TB0IN1/PH1 MAIN_VOL_MUTE - - O - - - O/L O/L Volume Mute control pin
32 TB1IN0/PH2 TUNER_RST - - O - - - O/L O/L TUNER Reset control pin
33 TXD2/PF0 IPOD_TX - - O - - - O/L O/L IPod DOCK TX communication line
34 RXD2/PF1 IPOD_RX - - I - - - I O/L IPod DOCK RX communication line
35 CTS2/SCLK2/PF2 INT_RX - - I - +3VHPu - I O/L HDMI INT interrupt
36 TB1IN1/PH3 INT2_RX - - I - +3VHPu - I O/L HDMI INT2 intreeupt
37 PB4 MAIN_VOL_DATA - - O - - - O/L O/L Volume Data line
38 TB0OUT/PI0 MAIN_VOL_CLK - - O - - - O/L O/L Volume CLK line
39 INT6/PJ6 WAKE_UP - - I - M3VPu - I I WAKE UP pin
40 TB1OUT/PI1 TUNER_CE - - O - - - O/L O/L TUNER CE pin
41 PB5 COMPO_SW2 - - O - - - O/L O/L COMPO_(Video) SW2 control pin
42 TB2OUT/PI2 HDMI_SDA - - I/O - - - O/L O/L HDMI SDATA
43 PB6 HDMI_SCL - - O - - - O/L O/L HDMI SCL
44 SDA1/SO1/PF4 TUNER_SDIO - - I/O - - - O/L O/L TUNER SDIO
45 SCL1/SI1/PF5 TUNER_SCLK - - O - - - O/L O/L TUNER SCLK
46 SCK1/PF6 HDMIOST_CS - - O - +3VHPu - O/L O/L Chip Select pin for HDMI OST
47 PB7 DIR_RST - - O - - - O/L O/L DIR Reset
48 TB3OUT/PI3 DIR_CE - - O - - - O/L O/L DIR Chip Select
49 INT1/PJ1 DIR_DOUT - - I - - - O/L O/L DIR Output Data
50 CEC/PK0 COMPO_SW1 - - O - M3VPu - O/L O/L COMPO_(Video) SW1 control pin
51 PK1/SCOUT/ALARM DSP_DIR_CLK - - O - - - O/L O/L DSP_DIR_CLK
52 PI4/TB4OUT DSP_DATA - - I/O - - - O/L O/L DSP DATA
53 PI5/TB5OUT DSP_CS - - O - D3VPu - O/L O/L DSP Chip Select
54 PB0/TDO/SWV DEBUG - - O - M3VPu - O/L O/L MICOM DEBUG
55 PA0/TMS/SWDIO DEBUG - - O - M3VPu - O/L O/L MICOM DEBUG
56 PA1/TCK/SWCLK DEBUG - - I - - - O/L O/L MICOM DEBUG
57 TEST3 TEST3 - - - - - - - - OPEN
58 PJ7/INT7 DSP_DIR_DATA - - O - - - O/L O/L DSP_DIR_DATA
59 PB1/TDI DEBUG - - O - M3VPu - - - MICOM DEBUG
60 PB2/TRS- DEBUG - - O - M3VPu - - - MICOM DEBUG
61 PF3/RXIN1 CVBS_SW4 - - O - - - O/L O/L CVBS(Video) SW4 control pin
62 DVCC DVCC - - - - - - - - 3.3V
63 DVSS DVSS - - - - - - - - Fixed GND
64 PA2/TRACECLK HDMI_SW - - O - - - O/L O/L HDMI Audio Data MCLK Select SW
65 PA3/TRACEDATA0 CVBS_SW1 - - O - - - O/L O/L CVBS(Video) SW1 control pin
66 PA4/TRACEDATA1 DSP_RST - - O - - - O/L O/L DSP Reset control pin
67 PA5/TRACEDATA2 DSP_MODE_SEL - - I - - - O/L O/L DSP_MODE_SEL
68 PA6/TRACEDATA3 CODEC_MUTE - - I/O - - - O/L O/L CODEC Mute Control control pin
69 PA7 HDMIOST_HOLD - - O - +3VHPu - O/L O/L HOLD pin for HDMI OST
70 PJ0/INT0 TUNER_INT - - I - - - I O/L TUNER INTERRUPT
71 CVCC CVCC - - - - - - - - 3.3V
72 X2 XOUT - - - - - - - - XOUT
73 CVSS CVSS - - - - - - - - Fixed GND
74 X1 XIN - - - - - - - - XIN
75 REGVSS REGVSS - - - - - - - - Fixed GND
76 REGVCC REGVCC - - - - - - - - 3.3V
77 XT1 NC - - - - - - - - OPEN
78 XT2 NC - - - - - - - - OPEN
79 PI6/TB4IN0 STANDBY_LEDR - - O - - - O/L O/L 2COLOR LED RED
80 NMI NMI - - - - M3VPu - - -
81 MODE MODE - - - - - - - - Fixed GND
82 RESET RESET - - I - - - - - RESET
To Next Page
Loading...
