Denon AVR-4520

224
ADV7850
Pin No. Mnemonic Description
V1 TX_2+ Digital Output Channel 2 true of the HDMI Tx.
V2
T
X_2- Digital Output Channel 2 complement of the HDMI Tx.
V3 GND Ground
V4 TX_DDC_SDA Serial data for DDC bus of HDMI Tx. TX_DDCA_SDA is 5 V tolerant.
V20 AVDD Video Analog supply voltage (1.8V)
V21 AVDD Video Analog supply voltage (1.8V)
V22 AVDD Video Analog supply voltage (1.8V)
V23 AVDD Video Analog supply voltage (1.8V)
W1
T
X_1+ Digital Output Channel 1 true of the HDMI Tx.
W2 TX_1- Digital Output Channel 1 complement of the HDMI Tx.
W3 GND Ground
W4
T
X_HPD Hot Plug Detect signal of the HDMI Tx.
W20 GND Ground
W21 AVOUT2 Analog Video Mux output 2
W22 AVIN9 Analog video mux input channel
W23 AVIN8 Analog video mux input channel
Y1 TX_0+ Digital Output Channel 0 true of the HDMI Tx.
Y2
T
X_0- Digital Output Channel 0 complement of the HDMI Tx.
Y3 GND Ground
Y4 GND Ground
Y5 A7 SDRAM address line
Y6 A3 SDRAM address line
Y7 A10 SDRAM address line
Y8 BA0 SDRAM block address signal
Y9 CKE SDRAM clock enable
Y10 GND Ground
Y11 DQ6 SDRAM data line
Y12 DQ7 SDRAM data line
Y13 DQ0 SDRAM data line
Y14 DQ8 SDRAM data line
Y15 UDQS SDRAM upper data strobe true signal
Y16 SDVDD Memory interface supply
Y17 SAVDD SDRAM interface supply
Y18
T
RI1 Digital input capable of slicing bi-level or tri-level input from SCART or D-Connector.
Y19
T
RI2 Digital input capable of slicing bi-level or tri-level input from SCART or D-Connector.
Y20 GND Ground
Y21 AVOUT1 Analog Video Mux output 1
Y22 SYNC3 This is a synchronization on green or luma input (SOG/SOY) used in embedded
synchronization mode.
Y23 AVIN7 Analog video mux input channel
AA1
T
X_C+ Digital Output clock true of the HDMI Tx.
AA2 TX_C- Digital Output clock complement of the HDMI Tx.
AA3 TX_AVDD HDMI Tx Analog Supply (1.8V)
AA4 GND Ground
AA5 A9 SDRAM address line
AA6 A5 SDRAM address line
AA7 A1 SDRAM address line
AA8 BA1 SDRAM block address signal
AA9 WE SDRAM write enable signal
AA10 GND Ground
AA11 DQ4 SDRAM data line
AA12 DQ5 SDRAM data line
AA13 DQ2 SDRAM data line
AA14 DQ11 SDRAM data line
AA15 UDQSN SDRAM upper data strobe compliment signal
AA16 SDVDD Memory interface supply
AA17 GND Ground
AA18 HS_IN1/TRI7 HS on Graphics Port. The HS input signal is used for 5-wire timing mode. This ball can
also be used as a trilevel/bilevel input on the SCART or D-terminal connector.
AA19 VS_IN1/TRI8 VS on Graphics Port. The VS input signal is used for 5-wire timing mode. This ball can
also be used as a trilevel/bilevel input on the SCART or D-terminal connector.
AA20 GND Ground
AA21
T
RI3 Digital input capable of slicing bi-level or tri-level input from SCART or D-Connector.
AA22 HS_IN2/TRI5
T
he HS input signal is used for 5-wire timing mode. This ball can also be used as a