Denon AVR-4520

27
1.3. Error display
See the following table for each "Error information" display and its explanation (status).
Display order is
q
,
w
,
e
,
r
,
t
,
y
,
u
,
i
,
o
.
Condition Status FL Display Trouble shooting
q
Firm Check
NG
Compared with the destination setting
on the board. This is displayed when the
model name or destination information
written into the rmware does not match.
(
b
1)
F I R M E R R O R
• Please check the
destination-resistors
(
R2009/R2010, HDMI B'D).
• Please write the rmware
of correct destination.
w
SUB NG
No response from SUB microcomputer.
S U B E R R O R 0 1
• Please check SUB (U2101)
and arroud circuits.
e
V-DECODER
NG-1
An error has occurred as a result of the
DDR memory communication test while
initializing Video Decoder (ADV7850).
V - D E C O D E R E R R 0 1
• Please check ADV7850
(U1102, HDMI B'D) and
arroud circuits.
V-DECODER
NG-2
No response from the DDR memory
communication test while initializing Video
Decoder (ADV7850).
V - D E C O D E R E R R 0 2
r
IP SCALER
NG
An error has occurred in the i/p Scaler
(ADV8003)initial settings. The error is a
DDR memory Loopback Test error.
I P S C A L E R E R R 0 1
• Please check ADV8003
(U1401, HDMI B'D) and
arroud circuits.
Testing writing data between IP SCALER
and DDR resulted in no response.
I P S C A L E R E R R 0 2
t
GUI Version
NG
Error occurs in GUI version and Main
μ-com version.(
b
2)
G U I V E R . E R R O R
• Please check the rmware
of correct version.
y
DIR NG
No response from DIR
D I R E R R O R 0 1
• Please check DIR
（
U103,
U104, HDMI B'D) and
around circuits.
u
DSP1 NG
When DSP1 code boot is performed, the
DSP FLAG0 port does not change to "H"
even if DSP reset is executed.
D S P 1 E R R O R 0 1
• Please check DSP1
（
U101,
DSP B'D) and around
circuits.
Before DSP1 command is issued, the
DSP BUSY port does not change to "L".
D S P 1 E R R O R 0 2
When DSP1 data read is performed,
executing WRITE="L" does not result in
ACK="H".
D S P 1 E R R O R 0 3
When DSP1 data read is performed,
executing REQ="L" does not result in
ACK="L".
D S P 1 E R R O R 0 4
When DSP1 data writing is performed,
executing WRITE="H" does not result in
ACK="H".
D S P 1 E R R O R 0 5
When DSP1 data writing is performed,
executing REQ="L" does not result in
ACK="L".
D S P 1 E R R O R 0 6
DSP2 NG
When DSP2 code boot is performed, the
DSP FLAG0 port does not change to "H"
even if DSP reset is executed.
D S P 2 E R R O R 0 1
• Please check DSP2
（
U201,
DSP B'D) and around
circuits.
Before DSP2 command is issued, the
DSP BUSY port does not change to "L".
D S P 2 E R R O R 0 2
When DSP2 data read is performed,
executing WRITE="L" does not result in
ACK="H".
D S P 2 E R R O R 0 3
When DSP2 data read is performed,
executing REQ="L" does not result in
ACK="L".
D S P 2 E R R O R 0 4
When DSP2 data writing is performed,
executing WRITE="H" does not result in
ACK="H".
D S P 2 E R R O R 0 5
When DSP2 data writing is performed,
executing REQ="L" does not result in
ACK="L".
D S P 2 E R R O R 0 6