Eaton EDR-5000 - Page 1015

EDR-5000 IM02602007E
Name Description
Logic.LE29.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE29.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE29.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE30.Gate Out Signal: Output of the logic gate
Logic.LE30.Timer Out Signal: Timer Output
Logic.LE30.Out Signal: Latched Output (Q)
Logic.LE30.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE30.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE30.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE30.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE31.Gate Out Signal: Output of the logic gate
Logic.LE31.Timer Out Signal: Timer Output
Logic.LE31.Out Signal: Latched Output (Q)
Logic.LE31.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE31.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE31.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE31.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE31.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE31.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE32.Gate Out Signal: Output of the logic gate
Logic.LE32.Timer Out Signal: Timer Output
Logic.LE32.Out Signal: Latched Output (Q)
Logic.LE32.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE32.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE32.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE33.Gate Out Signal: Output of the logic gate
Logic.LE33.Timer Out Signal: Timer Output
Logic.LE33.Out Signal: Latched Output (Q)
Logic.LE33.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE33.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE33.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE33.Gate In3-I State of the module input: Assignment of the Input Signal
www.eaton.com 1015