Eaton EDR-5000 - Page 1016

EDR-5000 IM02602007E
Name Description
Logic.LE33.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE33.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE34.Gate Out Signal: Output of the logic gate
Logic.LE34.Timer Out Signal: Timer Output
Logic.LE34.Out Signal: Latched Output (Q)
Logic.LE34.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE34.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE35.Gate Out Signal: Output of the logic gate
Logic.LE35.Timer Out Signal: Timer Output
Logic.LE35.Out Signal: Latched Output (Q)
Logic.LE35.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE35.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE35.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE36.Gate Out Signal: Output of the logic gate
Logic.LE36.Timer Out Signal: Timer Output
Logic.LE36.Out Signal: Latched Output (Q)
Logic.LE36.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE36.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE36.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE37.Gate Out Signal: Output of the logic gate
Logic.LE37.Timer Out Signal: Timer Output
Logic.LE37.Out Signal: Latched Output (Q)
Logic.LE37.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In4-I State of the module input: Assignment of the Input Signal
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