Eaton EDR-5000 - Page 660

EDR-5000 IM02602007E
Name Description
Logic.LE51.Gate Out Signal: Output of the logic gate
Logic.LE51.Timer Out Signal: Timer Output
Logic.LE51.Out Signal: Latched Output (Q)
Logic.LE51.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE52.Gate Out Signal: Output of the logic gate
Logic.LE52.Timer Out Signal: Timer Output
Logic.LE52.Out Signal: Latched Output (Q)
Logic.LE52.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE53.Gate Out Signal: Output of the logic gate
Logic.LE53.Timer Out Signal: Timer Output
Logic.LE53.Out Signal: Latched Output (Q)
Logic.LE53.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE54.Gate Out Signal: Output of the logic gate
Logic.LE54.Timer Out Signal: Timer Output
Logic.LE54.Out Signal: Latched Output (Q)
Logic.LE54.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE55.Gate Out Signal: Output of the logic gate
Logic.LE55.Timer Out Signal: Timer Output
Logic.LE55.Out Signal: Latched Output (Q)
Logic.LE55.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE56.Gate Out Signal: Output of the logic gate
Logic.LE56.Timer Out Signal: Timer Output
Logic.LE56.Out Signal: Latched Output (Q)
Logic.LE56.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE57.Gate Out Signal: Output of the logic gate
Logic.LE57.Timer Out Signal: Timer Output
Logic.LE57.Out Signal: Latched Output (Q)
Logic.LE57.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE58.Gate Out Signal: Output of the logic gate
Logic.LE58.Timer Out Signal: Timer Output
Logic.LE58.Out Signal: Latched Output (Q)
Logic.LE58.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE59.Gate Out Signal: Output of the logic gate
Logic.LE59.Timer Out Signal: Timer Output
Logic.LE59.Out Signal: Latched Output (Q)
Logic.LE59.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE60.Gate Out Signal: Output of the logic gate
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