Eaton EDR-5000 - Page 868

EDR-5000 IM02602007E
Programmable Logic Inputs
Name Description Assignment via
LE1.Gate In1-I State of the module input: Assignment of the Input Signal [Logic
/LE 1]
LE1.Gate In2-I State of the module input: Assignment of the Input Signal [Logic
/LE 1]
LE1.Gate In3-I State of the module input: Assignment of the Input Signal [Logic
/LE 1]
LE1.Gate In4-I State of the module input: Assignment of the Input Signal [Logic
/LE 1]
LE1.Reset Latch-I State of the module input: Reset Signal for the Latching [Logic
/LE 1]
Programmable Logic Outputs
Signal Description
LE1.Gate Out Signal: Output of the logic gate
LE1.Timer Out Signal: Timer Output
LE1.Out Signal: Latched Output (Q)
LE1.Out inverted Signal: Negated Latched Output (Q NOT)
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