8060A
Instruction Manual
4-6
4-5. A/D Conversion Cycle
The heart of the MAC is the dual-slope a/d converter. A block diagram of the
analog portion of the a/d converter is shown in Figure 4-2. The internal
buffer, integrator, and comparators work in conjunction with external
resistors and capacitors to convert the dc analog voltage to a digital number.
The internal switches are FET switches that are controlled by the
microcomputer and the MAC digital control logic. The switchable integrator
gain depends on the function and range selected.
The complete a/d measurement cycle is shown in Figure 4-3. It consists of
three consecutive time periods: autozero (AZ), integrate (INTEG) and read.
A fourth time period, overload (OL) is also used if an overrange reading is
taken. The total length of the measurement cycle is 400 ms. The length of the
integrate period is fixed at 100 ms. One hundred ms is a multiple of the
period of 50 Hz or 60 Hz power, which helps to reduce possible power line
noise that might interfere with the measurement. The waveform at the
INTEG capacitor is shown for three sample measurement readings: half-
scale, full-scale, and overrange.
The measurement cycle begins with the autozero period. The AZ switches
close, applying a ground reference as the input to the converter. Under ideal
conditions the output of the comparator would also go to zero. However,
input-offset voltage errors accumulate in the buffer amplifier loop, and
appear at the comparator output as an error voltage. To compensate for this
error, the error is impressed across the AZ capacitor where it is stored for the
remainder of the measurement cycle. The stored level is used to provide
offset voltage correction during the integrate and read periods.
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