Cinterion
®
LTE Terminals Hardware Interface Description
3.6 GPIO Interface
47
ELSxT_HID_v04 2018-09-04
Confidential / Preliminary
Page 37 of 102
3.6.3 I
2
C Interface
Two lines of the LTE Terminals‘ GPIO connector are I
2
C lines. I
2
C is a serial, 8-bit oriented data
transfer bus for bit rates up to 400kbps in Fast mode. It consists of two lines, the serial data line
I2CDAT and the serial clock line I2CCLK. The LTE Terminals‘ internal LTE module act as a
single master device, e.g. the clock I2CCLK is driven by the LTE module. I2CDAT is a bi-direc-
tional line. Each device connected to the bus is software addressable by a unique 7-bit ad-
dress, and simple master/slave relationships exist at all times. The LTE module operates as
master-transmitter or as master-receiver. An external application transmits or receives data
only on request of the module.
To configure and activate the I2C bus use the AT^SSPI command. Detailed information on the
AT^SSPI command as well explanations on the protocol and syntax required for data transmis-
sion can be found in [1].
With the external application, I2CDAT and I2CCLK lines need to be connected to a positive
supply voltage via a pull-up resistor. For electrical characteristics please refer to Table 23.
Note: Good care should be taken when connecting the I2C lines to the external application: The
wires of I2CCLK and I2CDAT should be equal in length and as short as possible.
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