Cinterion
®
LTE Terminals Hardware Interface Description
3.6 GPIO Interface
47
ELSxT_HID_v04 2018-09-04
Confidential / Preliminary
Page 39 of 102
3.6.5 PWM Interface
The GPIO6 and GPIO7 pins at the GPIO connector can be configured as Pulse Width Modu-
lation signals PWM1 and PWM2 by AT^SCFG command - see [1]. The PWM interface lines
are output lines and can be used, for example, to connect buzzers. The PWM1 line is shared
with GPIO7 and the PWM2 line is shared with GPIO6 (see also Table 14). GPIO and PWM
functionalities are mutually exclusive
1
.
3.6.6 Pulse Counter
The GPIO8 pin at the GPIO connector can be configured as pulse counter line COUNTER by
AT^SCFG command - see [1]. The pulse counter interface is an input line and can be used, for
example, as a clock (see also Table 14). GPIO and COUNTER functionalities are mutually ex-
clusive
1
.
3.6.7 Analog-to-Digital Converter (ADC)
ADC1_IN can be used for general purpose voltage measurements. For electrical characteris-
tics see Section 4.2.4. ADC1_IN is configured and read by the AT^SRADC command - see [1].
ADC1_IN, DSR0 and SPI functionalities are mutually exclusive.
3.6.8 DSR0 signal
The DSR0 line available at the RS-232 interface is also routed to the GPIO connector and avail-
able as a separate pin. For electrical characteristics see Section 4.2.4. DSR0 can be configured
by AT^SCFG command - see [1]. DSR0, ADC1_IN and SPI functionalities are mutually exclu-
sive.
1. Note: For the PWM interface and pulse counter to operate, the directions of the LTE Terminals‘ GPIO
level shifters must be set according to the defined directions of the PWM and COUNTER signals. See
Section 8.3.1.11 and Section 8.5 for more information on how to change level shifter directions.
To Next Page
Loading...
Need help?
General
