Holtek HT66F0175 - Page 139

Rev. 1.50 138 August 28, 2017 Rev. 1.50 139 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
SIMC0 Register
Bit 7 6 5 4 3 2 1 0
Name SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF
R/W R/W R/W R/W — R/W R/W R/W R/W
POR 1 1 1 — 0 0 0 0
Bit7~5 SIM2~SIM0:SIMOperatingModeControl
000:SPImastermode;SPIclockisf
SYS
/4
001:SPImastermode;SPIclockisf
SYS
/16
010:SPImastermode;SPIclockisf
SYS
/64
011:SPImastermode;SPIclockisf
TBC
100:SPImastermode;SPIclockisTM1CCRPmatchfrequency/2
101:SPIslavemode
110:I
2
Cslavemode
111:NonSIMfunction
ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.Aswellasselecting
iftheI
2
CorSPIfunction,theyareusedtocontroltheSPIMaster/Slaveselectionand
theSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbut
canalsobechosentobesourcedfromTM1.IftheSPISlaveModeisselectedthenthe
clockwillbesuppliedbyanexternalMasterdevice.
Bit4 Unimplemented,readas“0”
Bit3~2 SIMDEB1~SIMDEB0:I
2
CDebounceTimeSelection
00:Nodebounce
01:2systemclockdebounce
1x:4systemclockdebounce
Bit1 SIMEN:SIMEnableControl
0:Disable
1:Enable
Thebitistheoverallon/offcontrolfortheSIMinterface.WhentheSIMENbitis
clearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAand
SCLlineswilllosetheirSPIorI
2
CfunctionandtheSIMoperatingcurrentwillbe
reducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.Ifthe
SIMisconguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontents
oftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbit
changesfromlowtohighandshouldthereforeberstinitialisedbytheapplication
program.IftheSIMisconguredtooperateasanI
2
CinterfaceviatheSIM2~SIM0
bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI
2
Ccontrolbits
suchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebe
rstinitialisedbytheapplicationprogramwhiletherelevantI
2
CagssuchasHCF,
HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.
Bit0 SIMICF:SIMIncompleteFlag
0:SIMincompleteconditionnotoccurred
1:SIMincompleteconditionoccured
ThisbitisonlyavailablewhentheSIMisconguredtooperateinanSPIslavemode.
IftheSPIoperatesintheslavemodewiththeSIMENandCSENbitsbothbeingset
to1buttheSCSlineispulledhighbytheexternalmasterdevicebeforetheSPIdata
transferiscompletelynished,theSIMICFbitwillbesetto1togetherwiththeTRF
bit.Whenthisconditionoccurs,thecorrespondinginterruptwilloccuriftheinterrupt
functionisenabled.However,theTRFbitwillnotbesetto1iftheSIMICFbitisset
to1bysoftwareapplicationprogram.