EasyManua.ls Logo

Holtek HT66F0175 - Page 142

Default Icon
207 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Rev. 1.50 142 August 28, 2017 Rev. 1.50 143 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
I
2
C Bus Start Signal
TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI
2
Cbusandnotby
theslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI
2
Cbus.When
detected,thisindicatesthattheI
2
CbusisbusyandthereforetheHBBbitwillbeset.ASTART
conditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLline
remainshigh.
I
2
C Slave Address
ThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI
2
Cbus.
Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslave
devicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceiving
this7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutby
themastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI
2
Cbus
interruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,denes
theread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewill
thentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.Theslavedevicewillalsoset
thestatusagHAASwhentheaddressesmatch.
AsanI
2
Cbusinterruptcancomefromthreesources,whentheprogramenterstheinterrupt
subroutine,theHAASandSIMTOFbitsshouldbeexaminedtoseewhethertheinterruptsourcehas
comefromamatchingslaveaddress,thecompletionofadatabytetransferortheI
2
Cbustime-out
occurrence.Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmode
andthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummy
readfromtheSIMDregistertoreleasetheSCLline.
I
2
C Bus Read/Write Signal
TheSRWbitintheSIMC1registerdeneswhetherthemasterdevicewishestoreaddatafromthe
I
2
CbusorwritedatatotheI
2
Cbus.Theslavedeviceshouldexaminethisbittodetermineifitisto
beatransmitterorareceiver.IftheSRWagis“1”thenthisindicatesthatthemasterdevicewishes
toreaddatafromtheI
2
Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI
2
Cbusas
atransmitter.IftheSRWagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI
2
C
bus,thereforetheslavedevicemustbesetuptoreaddatafromtheI
2
Cbusasareceiver.
I
2
C Bus Slave Address Acknowledge Signal
Afterthemasterhastransmittedacallingaddress,anyslavedeviceontheI
2
Cbus,whose
owninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.The
acknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.Ifno
acknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemaster
toendthecommunication.WhentheHAASagishigh,theaddresseshavematchedandtheslave
devicemustchecktheSRWagtodetermineifitistobeatransmitterorareceiver.IftheSRWag
ishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1register
shouldbesetto“1”.IftheSRWagislow,thenthemicrocontrollerslavedeviceshouldbesetupas
areceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.

Table of Contents