Rev. 1.50 142 August 28, 2017 Rev. 1.50 143 August 28, 2017
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
I
2
C Bus Start Signal
TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI
2
Cbusandnotby
theslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI
2
Cbus.When
detected,thisindicatesthattheI
2
CbusisbusyandthereforetheHBBbitwillbeset.ASTART
conditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLline
remainshigh.
I
2
C Slave Address
ThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI
2
Cbus.
Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslave
devicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceiving
this7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutby
themastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI
2
Cbus
interruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,denes
theread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewill
thentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.Theslavedevicewillalsoset
thestatusagHAASwhentheaddressesmatch.
AsanI
2
Cbusinterruptcancomefromthreesources,whentheprogramenterstheinterrupt
subroutine,theHAASandSIMTOFbitsshouldbeexaminedtoseewhethertheinterruptsourcehas
comefromamatchingslaveaddress,thecompletionofadatabytetransferortheI
2
Cbustime-out
occurrence.Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmode
andthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummy
readfromtheSIMDregistertoreleasetheSCLline.
I
2
C Bus Read/Write Signal
TheSRWbitintheSIMC1registerdeneswhetherthemasterdevicewishestoreaddatafromthe
I
2
CbusorwritedatatotheI
2
Cbus.Theslavedeviceshouldexaminethisbittodetermineifitisto
beatransmitterorareceiver.IftheSRWagis“1”thenthisindicatesthatthemasterdevicewishes
toreaddatafromtheI
2
Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI
2
Cbusas
atransmitter.IftheSRWagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI
2
C
bus,thereforetheslavedevicemustbesetuptoreaddatafromtheI
2
Cbusasareceiver.
I
2
C Bus Slave Address Acknowledge Signal
Afterthemasterhastransmittedacallingaddress,anyslavedeviceontheI
2
Cbus,whose
owninternaladdressmatchesthecallingaddress,mustgenerateanacknowledgesignal.The
acknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.Ifno
acknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemaster
toendthecommunication.WhentheHAASagishigh,theaddresseshavematchedandtheslave
devicemustchecktheSRWagtodetermineifitistobeatransmitterorareceiver.IftheSRWag
ishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1register
shouldbesetto“1”.IftheSRWagislow,thenthemicrocontrollerslavedeviceshouldbesetupas
areceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.