Chapter 7 395
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
Bit 5 LADCEN Enables FADC memory for "writes". (Toggled
in conjunction with bit 0.)
1 Disables FADC memory for "writes".
0 Enables FADC memory for "writes".
Bit 6 LLOADADDR Enables load address counter.
1 "Writes" to the address counter disabled.
0 "Writes" to the address counter enabled.
Bit 7 LLOADPOST Enables load post-trigger counter.
1 "Writes" to the post-trigger counter disabled.
0 "Writes" to the post-trigger counter enabled.
Bit 8 LVTRIG_EN Enables digital video trigger on A16.
1 Digital video trigger disabled.
0 Digital video trigger enabled.
Bit 9 LREADCLK Clocks counters during "read" mode. Used to
load post-trigger counter or address counter.
Also used to post-increment address counter
following memory "reads".
1 Read clock disabled.
0 Read clock enabled.
Table 7-13 Control Word at Primary Address (U3 and U4)
Bit Mnemonic State Description
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