394 Chapter7
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
Table 7-13 Control Word at Primary Address (U3 and U4)
Bit Mnemonic State Description
Bit 0 WRITE Allows samples to be written to FADC
memory.
1 All on-board clocks running and samples
being written to FADC memory. (FADC
memory cannot be read by A2 controller in
this mode.)
0 All on-board clocks turned off and no
samples being written to FADC memory.
(FADC memory can be read by A2 controller.)
Bit 1 ARM Arms the FADC assembly for a trigger.
1 FADC assembly armed to accept trigger from
HSWP line or video trigger.
0 FADC assembly cannot be triggered.
Bit 2 GAINX2 Turns on X2 log expand amplifier.
1 A16U43 turned on. (5 dB/div or 1 dB/div
scale)
0 A16U43 turned off. (10 dB/div, 2 dB/div, or
linear scale)
Bit 3 VTRIG_POL Controls digital video trigger polarity.
1 Negative-edge video trigger
0 Positive-edge video trigger
Bit 4 LSAMPLE Enables sample detection mode.
1 Sample detection mode disabled.
Sample detection mode enabled
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