HP 8560E - Reference Clock (8560 EC); Clock and Sample Rate Generator

396 Chapter7
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
Bit
10
LREADMEM Enables read FADC memory.
1 Read FADC memory disabled.
0 Read FADC memory enabled.
Bit
11
LREADADDR Enables read trigger address latch.
1 "Reads" from trigger address latch disabled.
0 "Reads" from trigger address latch enabled.
Bit
12
LRATELATCH Enables load sample rate latch.
1 "Writes" to the sample rate latch are
disabled.
0 "Writes" to the sample rate latch are
enabled.
Bit
13
LRLSHSWP Releases HSWP strobe.
1 Release HSWP strobe disabled.
0 Release HSWP strobe enabled.
Bit
14
LLOADTRIG Enables load video trigger level.
1 Load digital video trigger level disabled.
0 Load digital video trigger level enabled.
Table 7-13 Control Word at Primary Address (U3 and U4)
Bit Mnemonic State Description